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SNLS472A January 2014 – June 2017 DS110DF1610

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

ABB|196
- MPBGAF3B

散热焊盘机械数据 (封装 | 引脚)

订购信息

1 Features

Pin-Compatible Family
- DS150DF1610: 12.5 - 15G
- DS125DF1610: 9.8 to 12.5G
- DS110DF1610: 8.5 – 11.3G
4x4 Analog Cross Point Switch for Each Quad
Fully-Adaptive CTLE
Self-Tuning DFE, With Optional Continuous Adaption
On-Chip, AC-coupling on Receive Inputs
Adjustable Transmit V_OD
Adjustable 3-Tap Transmit FIR Filter
Locks to Half/Quarter/Eighth Data Rates For Legacy Support
On-Chip Eye Monitor (EOM), PRBS Checker, PRBS Pattern Generator
Supports IEEE 1149.1 and 1149.6
Programmable Output Polarity Inversion
Input Signal Detection, CDR Lock Detection
Single 2.5-V ±5% Power Supply
SMBus-Based Register Configuration
Optional EEPROM Configuration
15-mm × 15-mm, 196-Pin FCBGA Package
Operating Temp Range : –10°C to +85°C

Typical Application Diagram

DS110DF1610 Bitmap_in_Schematic_SNLS472.gif

2 Description

The DS110DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning. The device includes a full adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10^-15.

Each channel of the DS110DF1610 independently locks to serial data at 8.5 to 11.3 Gbps and any supported sub-multiple. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream can be used as a reference clock to speed up the lock process. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS110DF1610.

Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.

A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DS110DF1610	FCBGA (196)	15.00 mm × 15.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

3 Revision History

Changes from * Revision (January 2014) to A Revision

Changed device status from PRODUCT PREVIEW to PRODUCTION DATAGo

4 Pin Configuration and Functions

Pin Descriptions

DS110DF1610, DS125DF1610 PIN NAME	DS150DF1610 PIN NAME	NO.	I/O TYPE	DESCRIPTION
HIGH-SPEED DIFFERENTIAL I/Os
RX_1A_P RX_1A_N	RX_0_0P RX_0_0N	A14 B14	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_0B_P Rx_0B_N	RX_0_1P RX_0_1N	A12 B12	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_0A_P RX_0A_N	RX_0_2P RX_0_2N	A10 B10	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_2A_P RX_2A_N	RX_0_3P RX_0_3N	C13 D13	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_1B_P RX_1B_N	RX_0_4P RX_0_4N	C11 D11	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_3A_P RX_3A_N	RX_0_5P RX_0_5N	E14 F14	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_2B_P RX_2B_N	RX_0_6P RX_0_6N	E12 F12	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_4A_P RX_4A_N	RX_0_7P RX_0_7N	G13 H13	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_3B_P RX_3B_N	RX_1_0P RX_1_0N	G11 H11	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_4B_P Rx_4B_N	RX_1_1P RX_1_1N	J14 K14	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_5A_P RX_5A_N	RX_1_2P RX_1_2N	J12 K12	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_5B_P RX_5B_N	RX_1_3P RX_1_3N	L13 M13	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_6A_P RX_6A_N	RX_1_4P RX_1_4N	L11 M11	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_6B_P RX_6B_N	RX_1_5P RX_1_5N	N14 P14	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_7A_P RX_7A_N	RX_1_6P RX_1_6N	N12 P12	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
RX_7B_P RX_7B_N	RX_1_7P RX_1_7N	N10 P10	I, CML	Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs.
TX_1A_P TX_1A_N	TX_0_0P TX_0_0N	A1 B1	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_0B_P TX_0B_N	TX_0_1P TX_0_1N	A3 B3	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_0A_P TX_0A_N	TX_0_2P TX_0_2N	A5 B5	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_2A_P TX_2A_N	TX_0_3P TX_0_3N	C2 D2	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_1B_P TX_1B_N	TX_0_4P TX_0_4N	C4 D4	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_3A_P TX_3A_N	TX_0_5P TX_0_5N	E1 F1	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_2B_P TX_2B_N	TX_0_6P TX_0_6N	E3 F3	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_4A_P TX_4A_N	TX_0_7P TX_0_7N	G2 H2	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_3B_P TX_3B_N	TX_1_0P TX_1_0N	G4 H4	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_4B_P TX_4B_N	TX_1_1P TX_1_1N	J1 K1	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_5A_P TX_5A_N	TX_1_2P TX_1_2N	J3 K3	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_5B_P TX_5B_N	TX_1_3P TX_1_3N	L2 M2	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_6A_P TX_6A_N	TX_1_4P TX_1_4N	L4 M4	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_6B_P TX_6B_N	TX_1_5P TX_1_5N	N1 P1	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_7A_P TX_7A_N	TX_1_6P TX_1_6N	N3 P3	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
TX_7B_P TX_7B_N	TX_1_7P TX_1_7N	N5 P5	O, CML	Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching.
CLOCK PINS
REF_CLK_P REF_CLK_N		P7 P8	I, LVDS/LVCMOS	Inverting and non-inverting CML-compatible differential inputs for 25 MHz, 125 MHz, or 312.5 MHz clock. When configured for single-ended input operation, apply LVCMOS ref clock to REF_CLK_P and float REF_CLK_N. Single-ended signals should be DC coupled.
CLK_MON_P CLK_MON_N		A7 A8	O, LVDS	Inverting and non-inverting CML-compatible differential outputs to monitor system differential clock. When daisy chaining to another retimer the output frequency should be set to 25 MHz or 125 MHz.
SMBUS INTERFACE
SDA_IO		M7	I/O, Open Drain	Data Input / Open Drain Output External pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant.
SCL_IO		L6	I/O, Open Drain	Clock input/output, Pin is 3.3 V LVCMOS Tolerant EEPROM configuration (SMBus Master mode) will be available in final silicon
JTAG INTERFACE
TMS_IO		B7	I, LVCMOS	JTAG Test Mode Select, internal pull-up
TDO_IO		C7	O, LVCMOS	JTAG Test Data Out
TRST_IO		C8	I, LVCMOS	JTAG Test Reset, internal pull-up
TCK_IO		D6	I, LVCMOS	JTAG Test clock, internal pull-up
TDI_IO		D7	I, LVCMOS	JTAG Test Data Input, internal pull-up
OTHER PINS
RESET_IO		L8	I, LVCMOS	Resets registers and state machines on rising edge. Expected pulse of 10µs.
INTERR_IO		M8	O, Open Drain	Active Low interrupt signal. Pin goes low when an interrupt event occurs. Interrupts must be enabled via SMBus.
ADDR0 (GPIO0)		B6	I/O, LVCMOS	4 level input strap pin for SMBus address code LSB. Standard LVCMOS output.
ADDR1(GPIO1)		D5	I/O, LVCMOS	4 level input strap pin for SMBus address code MSB. Standard LVCMOS output.
READ_EN (GPIO2)		G5	I/O, LVCMOS	Tie low for SMBus slave mode operation. Pin has internal pull down.
ALL_DONE (GPIO3)		L5	I/O, LVCMOS	EEPROM load status. Pin goes LOW when EEPROM load is complete.
EN_SMB (SCAN_MODE)		N8	I, LVCMOS	Connect to GND through ≤1kΩ resistor for SMBus slave operation. Connect to VDD through ≤1kΩ resistor for EEPROM configuration
POWER
VDD		E5, E7, E9, E10, F5, F6, F8, F10, G7, G9, H6, H8, J5, J7, J9, J10, K5, K6, K8, K10	Power	VDD = 2.5 V +/- 5%
GND		A2, A4, A6, A9, A11, A13, B2, B4, B9, B11, B13, C1, C3, C5, C10, C12, C14, D1, D3, D10, D12, D14, E2, E4, E6, E8, E11, E13, F2, F4, F7, F9, F11, F13, G1, G3, G6, G8, G10, G12, G14, H1, H3, H5, H7, H9, H10, H12, H14, J2, J4, J6, J8, J11, J13, K2, K4, K7, K9, K11, K13, L1, L3, L10, L12, L14, M1, M3, M5, M10, M12, M14, N2, N4, N6, N9, N11, N13, P2, P4, P6, P9, P11, P13	Power	Ground reference
N/C		B8, C6, C9, D8, D9, L7, L9, M6, M9, N7		No Connect, leave floating