ZHCSDR9D July 2012 – May 2015 DS125BR401
PRODUCTION DATA.
- 1 特性
- 2 应用范围
- 3 说明
- 4 典型应用
- 5 修订历史记录
- 6 说明（续）
- 7 Pin Configuration and Functions
- 8 Specifications
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文档支持
- 14机械、封装和可订购信息
8 Specifications
8.1 Absolute Maximum Ratings(1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply Voltage (VDD - 2.5 V) | –0.5 | 2.75 | V | |
| Supply Voltage (VIN - 3.3 V) | –0.5 | 4 | V | |
| LVCMOS Input/Output Voltage | –0.5 | 4 | V | |
| CML Input Voltage | –0.5 | (VDD + 0.5) | V | |
| CML Input Current | –30 | 30 | mA | |
| Junction Temperature | 125 | °C | ||
| Lead Temperature Range Soldering (4 sec.)(2) | 260 | °C | ||
| Storage Temperature, Tstg | –40 | 125 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specifications: See application note SNOA549.
8.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±5000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1000 | |||
| Machine model (MM), JESD22-A115-A | ±150 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute maximum numbers are specified for a junction temperature range of –40°C to 125°C. Models are validated to maximum operating voltages only.| MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|
| Supply Voltage (2.5-V mode) | 2.375 | 2.5 | 2.625 | V |
| Supply Voltage (3.3-V mode) | 3.0 | 3.3 | 3.6 | V |
| Ambient Temperature | –40 | 25 | 85 | °C |
| SMBus (SDA, SCL) | 3.6 | V | ||
| Supply Noise up to 50 MHz(1) | 100 | mVp-p |
(1) Allowed supply noise (mVp-p sine wave) under typical conditions.
8.4 Thermal Information
| THERMAL METRIC(1) | DS125BR401 | UNIT | |
|---|---|---|---|
| NJY [WQFN] | |||
| 54 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 26.6 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 10.8 | °C/W |
| RθJB | Junction-to-board thermal resistance | 4.4 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
| ψJB | Junction-to-board characterization parameter | 4.3 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.5 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
8.5 Electrical Characteristics
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER | ||||||
| PD | Power Dissipation | VDD = 2.5-V supply, EQ Enabled, VOD = 1 Vp-p, RXDET = 1, PWDN = 0 |
500 | 700 | mW | |
| VIN = 3.3-V supply, EQ Enabled, VOD = 1 Vp-p, RXDET = 1, PWDN = 0 |
660 | 900 | ||||
| LVCMOS / LVTTL DC SPECIFICATIONS | ||||||
| VIH25 | High Level Input Voltage | 2.5-V Mode | 2.0 | VDD | V | |
| VIH33 | High Level Input Voltage | 3.3-V Mode | 2.0 | VIN | V | |
| VIL | Low Level Input Voltage | 0 | 0.8 | V | ||
| VOH | High Level Output Voltage (ALL_DONE pin) |
Ioh = –4 mA | 2.0 | V | ||
| VOL | Low Level Output Voltage (ALL_DONE pin) |
Iol = 4 mA | 0.4 | V | ||
| IIH | Input High Current (PWDN pin) | VIN = 3.6 V, LVCMOS = 3.6 V |
–15 | 15 | µA | |
| Input High Current with internal resistors (4-level input pin) |
20 | 150 | ||||
| IIL | Input Low Current (PWDN pin) | VIN = 3.6 V, LVCMOS = 0 V |
–15 | 15 | µA | |
| Input Low Current with internal resistors (4-level input pin) |
–160 | –40 | ||||
| CML RECEIVER INPUTS (IN_N+, IN_N-) | ||||||
| RLRX-DIFF | RX Differential return loss | 0.05 - 7.5 GHz | –15 | dB | ||
| 7.5 - 15 GHz | –5 | |||||
| RLRX-CM | RX Common mode return loss | 0.05 - 5 GHz | –10 | dB | ||
| ZRX-DC | RX DC common mode impedance | Tested at VDD = 2.5 V | 40 | 50 | 60 | Ω |
| ZRX-DIFF-DC | RX DC differential mode impedance | Tested at VDD = 2.5 V | 80 | 100 | 120 | Ω |
| VRX-DIFF-DC | Differential RX peak-to-peak voltage (VID) | Tested at pins | 1.2 | V | ||
| VRX-SIGNAL-DET-DIFF-PP | Signal detect assert level for active data signal | SD_TH = F (float), 0101 pattern at 8 Gbps | 180 | mVp-p | ||
| VRX-IDLE-DET-DIFF-PP | Signal detect deassert level for electrical idle | SD_TH = F (float), 0101 pattern at 8 Gbps | 110 | mVp-p | ||
| HIGH SPEED OUTPUTS | ||||||
| VTX-DIFF-PP | Output Voltage Differential Swing | Differential measurement with Out_n+ and OUT_n-, terminated by 50 Ω to GND, AC-Coupled, VID = 1 Vp-p, DEM0 = 1, DEM1 = 0(2) |
0.8 | 1 | 1.2 | Vp-p |
| VTX-DE-RATIO_3.5 | TX de-emphasis ratio | VOD = 1 Vp-p, DEM0 = 0, DEM1 = R, PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps) |
–3.5 | dB | ||
| VTX-DE-RATIO_6 | TX de-emphasis ratio | VOD = 1 Vp-p, DEM0 = R, DEM1 = R, PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps) |
–6 | dB | ||
| TTX-DJ | Deterministic Jitter | VID = 800 mV, PRBS15 pattern, 8.0 Gbps, VOD = 1 V, EQ = 0x00, DE = 0 dB, (no input or output trace loss) | 0.05 | UIpp | ||
| TTX-RJ | Random Jitter | VID = 800 mV, 0101 pattern, 8.0 Gbps, VOD = 1 V, EQ = 0x00, DE = 0 dB, (no input or output trace loss) | 0.3 | ps RMS | ||
| TTX-RISE-FALL | Transmitter rise/fall time | 20% to 80% of differential output voltage | 35 | 45 | ps | |
| TRF-MISMATCH | Transmitter rise/fall mismatch | 20% to 80% of differential output voltage | 0.01 | 0.1 | UI | |
| RLTX-DIFF | TX Differential return loss | 0.05 - 7.5 GHz | –15 | dB | ||
| 7.5 - 15 GHz | –5 | |||||
| RLTX-CM | TX Common mode return loss | 0.05 - 5 GHz | –10 | dB | ||
| ZTX-DIFF-DC | DC differential TX impedance | 100 | Ω | |||
| VTX-CM-AC-PP | TX AC common mode voltage | VOD = 1 Vp-p, DEM0 = 1, DEM1 = 0 |
100 | mVp-p | ||
| ITX-SHORT | Transmitter short circuit current limit | Total current the transmitter can supply when shorted to VDD or GND | 20 | mA | ||
| VTX-CM-DC-ACTIVE-IDLE-DELTA | Absolute delta of DC common mode voltage during L0 and electrical idle | 100 | mV | |||
| VTX-CM-DC-LINE-DELTA | Absolute delta of DC common mode voltage between TX+ and TX- | 25 | mV | |||
| TTX-IDLE-DATA | Max time to transition to valid differential signal after idle | VID = 1 Vp-p, 8 Gbps | 3.5 | ns | ||
| TTX-DATA-IDLE | Max time to transition to idle after differential signal | VID = 1 Vp-p, 8 Gbps | 6.2 | ns | ||
| TPDEQ | Differential propagation delay | EQ = 00(1) | 200 | ps | ||
| TLSK | Lane-to-lane skew | T = 25°C, VDD = 2.5 V | 25 | ps | ||
| TPPSK | Part-to-part propagation delay skew | T = 25°C, VDD = 2.5 V | 40 | ps | ||
| EQUALIZATION | ||||||
| DJE1 | Residual deterministic jitter at 12 Gbps | 30” 5mils FR4, VID = 0.6 Vp-p, PRBS15, EQ = 0x07, DEM = 0 dB |
0.18 | UIpp | ||
| DJE2 | Residual deterministic jitter at 8 Gbps | 30” 5mils FR4, VID = 0.6 Vp-p, PRBS15, EQ = 0x07, DEM = 0 dB |
0.11 | UIpp | ||
| DJE3 | Residual deterministic jitter at 5 Gbps | 30” 5mils FR4, VID = 0.6 Vp-p, PRBS15, EQ = 0x07, DEM = 0 dB |
0.07 | UIpp | ||
| DJE4 | Residual deterministic jitter at 12 Gbps | 5-meter 30-AWG cable, VID = 0.6 Vp-p, PRBS15, EQ = 0x07, DEM = 0 dB |
0.25 | UIpp | ||
| DJE5 | Residual deterministic jitter at 12 Gbps | 8-meter 30-AWG cable, VID = 0.6 Vp-p, PRBS15, EQ = 0x0F, DEM = 0 dB |
0.33 | UIpp | ||
| DE-EMPHASIS — PCIe Gen-1 or PCIe Gen-2 and SAS/SATA (up to 6 Gbps) | ||||||
| DJD1 | Residual deterministic jitter at 12 Gbps |
Input Channel: 20" 5mils FR4, Output Channel: 10” 5mils FR4,VID = 0.6 Vp-p, PRBS15, EQ = 0x03, VOD = 1 Vp-p, DEM = −3.5 dB |
0.1 | UIpp | ||
(1) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the longest propagation delays.
(2) In PCIe Gen-3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output VOD level set by DEMA/B[1:0] in this MODE is dependent on the VID level and the frequency content. The DS125BR401 repeater is designed to be nonlimiting in this MODE, so the TX-FIR (de-emphasis) is passed to the RX to support the handshake negotiation link training.
8.6 Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SERIAL BUS INTERFACE DC SPECIFICATIONS | ||||||
| VIL | Data, Clock Input Low Voltage | 0.8 | V | |||
| VIH | Data, Clock Input High Voltage | 2.1 | 3.6 | V | ||
| IPULLUP | Current Through Pullup Resistor or Current Source | High Power Specification | 4 | mA | ||
| VDD | Nominal Bus Voltage | 2.375 | 3.6 | V | ||
| ILEAK-Bus | Input Leakage Per Bus Segment | See(1) | –200 | 200 | µA | |
| ILEAK-Pin | Input Leakage Per Device Pin | –15 | µA | |||
| CI | Capacitance for SDA and SCL | See(1)(2) | 10 | pF | ||
| RTERM | External Termination Resistance pull to VDD = 2.5 V ± 5% OR 3.3 V ± 10% | Pullup VDD = 3.3 V(1)(2)(3) | 2000 | Ω | ||
| Pullup VDD = 2.5 V(1)(2)(3) | 1000 | |||||
| SERIAL BUS INTERFACE TIMING SPECIFICATIONS | ||||||
| FSMB | Bus Operating Frequency | ENSMB = VDD (Slave Mode) | 400 | kHz | ||
| ENSMB = FLOAT (Master Mode) | 280 | 400 | 520 | |||
| TBUF | Bus Free Time Between Stop and Start Condition | 1.3 | µs | |||
| THD:STA | Hold time after (Repeated) Start Condition. After this period, the first clock is generated. | At IPULLUP, Max | 0.6 | µs | ||
| TSU:STA | Repeated Start Condition Setup Time | 0.6 | µs | |||
| TSU:STO | Stop Condition Setup Time | 0.6 | µs | |||
| THD:DAT | Data Hold Time | 0 | ns | |||
| TSU:DAT | Data Setup Time | 100 | ns | |||
| TLOW | Clock Low Period | 1.3 | µs | |||
| THIGH | Clock High Period | See(4) | 0.6 | 50 | µs | |
| tF | Clock/Data Fall Time | See(4) | 300 | ns | ||
| tR | Clock/Data Rise Time | See(4) | 300 | ns | ||
| tPOR | Time in which a device must be operational after power-on reset | See(4)(5) | 500 | ms | ||
(1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400 pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details.
(5) Ensured by Design. Parameter not tested in production.
Figure 1. CML Output and Rise and FALL Transition Time
Figure 2. Propagation Delay Timing Diagram
Figure 3. Transmit IDLE-DATA and DATA-IDLE Response Time
Figure 4. SMBus Timing Parameters
8.7 Typical Characteristics
Figure 5. Power Dissipation (PD) vs Output Differential Voltage (VOD)
Figure 7. Output Differential Voltage (VOD = 1 Vp-p) vs Temperature
Figure 6. Output Differential Voltage (VOD = 1 Vp-p) vs Supply Voltage (VDD)