ZHCSDR9D July 2012 – May 2015 DS125BR401
PRODUCTION DATA.
- 1 特性
- 2 应用范围
- 3 说明
- 4 典型应用
- 5 修订历史记录
- 6 说明（续）
- 7 Pin Configuration and Functions
- 8 Specifications
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文档支持
- 14机械、封装和可订购信息
9 Detailed Description
9.1 Overview
The DS125BR401 device compensates for lossy printed-circuit-board (PCB) backplanes and balanced cables.
The DS125BR401 compensates for lossy FR-4 PCB backplanes and balanced cables. The DS125BR401 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and SMBus Master Mode (ENSMB = float) to load register informations from external EEPROM; refer to SMBUS Master Mode for additional information.
9.2 Functional Block Diagram
9.3 Feature Description
The 4-level input pins use a resistor divider to help set the 4 valid levels and provide a wider range of control settings when ENSMB=0. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the package pin. These resistors, together with the external resistor connection combine to achieve the desired voltage level. Using the 1-kΩ pullup, 1-kΩ pulldown, no connect, and 20-kΩ pulldown provide the optimal voltage levels for each of the four input states.
Table 1. 4–Level Control Pin Settings
| LEVEL | SETTING | 3.3-V MODE | 2.5-V MODE |
|---|---|---|---|
| 0 | Tie 1 kΩ to GND | 0.10 V | 0.08 V |
| R | Tie 20 kΩ to GND | 1/3 × VIN | 1/3 × VDD |
| Float | Float (leave pin open) | 2/3 × VIN | 2/3 × VDD |
| 1 | Tie 1 kΩ to VIN or VDD | VIN – 0.05 V | VDD – 0.04 V |
9.3.1 Typical 4-Level Input Thresholds
- Level 1 - 2 = 0.2 × VIN or VDD
- Level 2 - 3 = 0.5 × VIN or VDD
- Level 3 - 4 = 0.8 × VIN or VDD
To minimize the start-up current associated with the integrated 2.5-V regulator, TI recommends using the 1-kΩ pullup and pulldown resistors. If several 4-level inputs require the same setting, it is possible to combine two or more 1-kΩ resistors into a single lower value resistor. As an example; combining two inputs with a single 500-Ω resistor is a good way to save board space.
9.4 Device Functional Modes
9.4.1 Pin Control Mode
When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected through pin for each side independently. When de-emphasis is asserted VOD is automatically adjusted per Table 3. For PCIe applications, the RXDET pins provides automatic and manual control for input termination (50 Ω or >50 kΩ). MODE setting is also pin controllable with pin selections (PCIe Gen-1, PCIe Gen-2, auto detect, and PCIe Gen-3). The receiver electrical idle detect threshold is also adjustable through the SD_TH pin.
9.4.2 SMBUS Mode
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins (MODE, RXDET and SD_TH) remain active unless their respective registers are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low (pin mode). On power up and when ENSMB is driven low all registers are reset to their default state. If PWDN is asserted while ENSMB is high, the registers retain their current state.
Equalization settings accessible through the pin controls were chosen to meet the needs of most high speed applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed through the SMBus registers. Each input has a total of 256 possible equalization settings. System Management Bus (SMBus) and Configuration Registers show the 16 setting when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-emphasis levels are set by registers.
9.5 Programming
9.5.1 PCIe Signal Integrity
When using the DS125BR401 in PCIe Gen-3 systems, there are specific signal integrity settings to ensure signal integrity margin. The settings were optimized by extensive testing. Contact your field representative for more information regarding the testing completed to achieve these settings.
For tuning the in the downstream direction (from CPU to EP).
- EQ: use the guidelines outlined in Table 2.
- De-Emphasis: use the guidelines outlined in Table 3.
- VOD: use the guidelines outlined in Table 3.
For tuning in the upstream direction (from EP to CPU).
- EQ: use the guidelines outlined in Table 2.
- De-Emphasis:
- For trace lengths < 15 in set to –3.5 dB
- For trace lengths > 15 in set to –6 dB
- VOD: set to 900 mV
Table 2. Equalizer Settings
| LEVEL | EQA1 EQB1 |
EQA0 EQB |
EQ – 8 bits [7:0] | dB at 1.5 GHz |
dB at 2.5 GHz |
dB at 4 GHz |
dB at 6 GHz |
SUGGESTED USE(1) |
|---|---|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 0000 0000 = 0x00 | 2.5 | 3.5 | 3.8 | 3.1 | FR4 < 5-inch trace |
| 2 | 0 | R | 0000 0001 = 0x01 | 3.8 | 5.4 | 6.7 | 6.7 | FR4 5- to 10-inch trace |
| 3 | 0 | Float | 0000 0010 = 0x02 | 5 | 7 | 8.4 | 8.4 | FR4 10-inch trace |
| 4 | 0 | 1 | 0000 0011 = 0x03 | 5.9 | 8 | 9.3 | 9.1 | FR4 15- to 20-inch trace |
| 5 | R | 0 | 0000 0111 = 0x07 | 7.4 | 10.3 | 12.8 | 13.7 | FR4 20- to 30-inch trace |
| 6 | R | R | 0001 0101 = 0x15 | 6.9 | 10.2 | 13.9 | 16.2 | FR4 25- to 30-inch trace |
| 7 | R | Float | 0000 1011 = 0x0B | 9 | 12.4 | 15.3 | 15.9 | FR4 25- to 30-inch trace |
| 8 | R | 1 | 0000 1111 = 0x0F | 10.2 | 13.8 | 16.7 | 17 | 8-m, 30-AWG cable |
| 9 | Float | 0 | 0101 0101 = 0x55 | 8.5 | 12.6 | 17.5 | 20.7 | > 8-m cable |
| 10 | Float | R | 0001 1111 = 0x1F | 11.7 | 16.2 | 20.3 | 21.8 | |
| 11 | Float | Float | 0010 1111 = 0x2F | 13.2 | 18.3 | 22.8 | 23.6 | |
| 12 | Float | 1 | 0011 1111 = 0x3F | 14.4 | 19.8 | 24.2 | 24.7 | |
| 13 | 1 | 0 | 1010 1010 = 0xAA | 14.4 | 20.5 | 26.4 | 28 | |
| 14 | 1 | R | 0111 1111 = 0x7F | 16 | 22.2 | 27.8 | 29.2 | |
| 15 | 1 | Float | 1011 1111 = 0xBF | 17.6 | 24.4 | 30.2 | 30.9 | |
| 16 | 1 | 1 | 1111 1111 = 0xFF | 18.7 | 25.8 | 31.6 | 31.9 |
(1) Cable and FR4 lengths are for reference only. FR4 lengths based on a 100-Ω differential stripline with 5-mil traces and 8-mil trace separation. Optimal EQ setting should be determined through simulation and prototype verification.
Table 3. Output Voltage and De-Emphasis Settings
| LEVEL | DEMA1 DEMB1 |
DEMA0 DEMB0 |
VOD Vp-p | DEM dB(1) | INNER AMPLITUDE Vp-p |
SUGGESTED USE(2) |
|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 0.8 | 0 | 0.8 | FR4 <5-inch trace |
| 2 | 0 | R | 0.9 | 0 | 0.9 | FR4 <5-inch trace |
| 3 | 0 | Float | 0.9 | –3.5 | 0.6 | FR4 10-inch trace |
| 4 | 0 | 1 | 1 | 0 | 1 | FR4 <5-inch trace |
| 5 | R | 0 | 1 | –3.5 | 0.7 | FR4 10-inch trace |
| 6 | R | R | 1 | –6 | 0.5 | FR4 15-inch trace |
| 7 | R | Float | 1.1 | 0 | 1.1 | FR4 <5-inch trace |
| 8 | R | 1 | 1.1 | –3.5 | 0.7 | FR4 10-inch trace |
| 9 | Float | 0 | 1.1 | –6 | 0.6 | FR4 15-inch trace |
| 10 | Float | R | 1.2 | 0 | 1.2 | FR4 <5-inch trace |
| 11 | Float | Float | 1.2 | –3.5 | 0.8 | FR4 10-inch trace |
| 12 | Float | 1 | 1.2 | –6 | 0.6 | FR4 15-inch trace |
| 13 | 1 | 0 | 1.3 | 0 | 1.3 | FR4 <5-inch trace |
| 14 | 1 | R | 1.3 | –3.5 | 0.9 | FR4 10-inch trace |
| 15 | 1 | Float | 1.3 | –6 | 0.7 | FR4 15-inch trace |
| 16 | 1 | 1 | 1.3 | –9 | 0.5 | FR4 20-inch trace |
(1) The VOD output amplitude and DEM de-emphasis levels are set with the DEMA/B[1:0] pins.
The de-emphasis levels are also available in PCIe Gen-3 mode when MODE = 1 (tied to VDD).
The de-emphasis levels are also available in PCIe Gen-3 mode when MODE = 1 (tied to VDD).
(2) FR4 lengths are for reference only. FR4 lengths based on a 100-Ω differential stripline with 5-mil traces and 8-mil trace separation. Optimal DEM settings should be determined through simulation and prototype verification.
Table 4. RX-Detect Settings
| PWDN (PIN 52) |
RXDET (PIN 22) |
SMBus REG bit[3:2] |
INPUT TERMINATION | RECOMMENDED USE | COMMENTS |
|---|---|---|---|---|---|
| 0 | 0 | 00 | Hi-Z | X | Manual RX-Detect, input is high impedance mode |
| 0 | Tie 20 kΩ to GND |
01 | Pre Detect: Hi-Z Post Detect: 50 Ω |
PCIe only | Auto RX-Detect, outputs test every 12 msec for 600 msec then stops; termination is Hi-Z until RX detection; once detected input termination is 50 Ω Reset function by pulsing PWDN high for 5 usec then low again |
| 0 | Float (Default) |
10 | Pre Detect: Hi-Z Post Detect: 50 Ω |
PCIe only | Auto RX-Detect, outputs test every 12 msec until detection occurs; termination is Hi-Z until RX detection; once detected input termination is 50 Ω |
| 0 | 1 | 11 | 50 Ω | All Others | Manual RX-Detect, input is 50 Ω |
| 1 | X | High Impedance | X | Power-down mode, input is Hi-Z, output drivers are disabled Used to reset RX-Detect State Machine when held high for 5 usec |
9.5.1.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
Unlike PCIe systems, SAS/SATA (up to 6 Gbps) systems use a low speed Out-Of-Band or OOB communications sequence to detect and communicate between Controllers/Expanders and target drives. This communication eliminates the need to detect for endpoints like PCIe. For SAS/SATA systems, TI recommends tying the RXDET pin high. This will ensure any OOB sequences sent from the Controller/Expander will reach the target drive without any additional latency due to the termination detection sequence defined by PCIe.
Table 5. Signal Detect Threshold Level(1)
| SD_TH (PIN 26) | SMBus REG bit [3:2] and [1:0] | ASSERT LEVEL (TYP) | DEASSERT LEVEL (TYP) |
|---|---|---|---|
| 0 | 10 | 210 mVp-p | 150 mVp-p |
| R | 01 | 160 mVp-p | 100 mVp-p |
| F (default) | 00 | 180 mVp-p | 110 mVp-p |
| 1 | 11 | 190 mVp-p | 130 mVp-p |
(1) VDD = 2.5V, 25°C and 0101 pattern at 8 Gbps
9.5.1.1.1 Signal Detect Control for Datarates Above 8 Gbps
Signal detect bandwidth limitations combined with high levels of signal attenuation can result in intermittent data loss above 8 Gbps. This data loss can be eliminated by disabling automatic detection and forcing the Signal Detect function to be always "on". This programming requires SMBus control over the DS125BR401 to be present. The Signal Detect function is controlled for each channel independently. The register programming sequence is shown below:
- Write register 0x06 = 0x18 //* Enable SMBus register programming
- Write registers 0x0D[1]= 1'b, 0x14[1] = 1'b, 0x1B[1] = 1'b, 0x22[1] = 1'b //* CH0 - CH3
- Write registers 0x2A[1]= 1'b, 0x31[1] = 1'b, 0x38[1] = 1'b, 0x3F[1] = 1'b //* CH4 - CH7
Table 6. MODE Operation with Pin Control
| MODE (PIN 21) |
Driver Characteristics | PCIe | SAS SATA |
10G-KR | 10GbE | CPRI OBSAI |
SRIO (R)XAUI |
Interlaken Infiniband |
|---|---|---|---|---|---|---|---|---|
| 0 | Limiting | X | X | X | X | X | ||
| R | Nonlimiting without DE | |||||||
| F (default) | Automatic | X | ||||||
| 1 | Nonlimiting with DE | X |
Note: Automatic operation allows input to sense the incoming data rate and use a Nonlimiting output driver for operation at or above 8 Gbps.
Note: SAS/SATA up to 6 Gbps.
9.5.1.2 MODE Operation With SMBus Registers
When in SMBus mode (Slave or Master), the MODE pin retains control of the output driver characteristics. In order to override this control function, Register 0x08[2] must be written with a "1". Writing this bit enables MODE control of each channel individually using the channel registers defined in Table 7.
9.5.2 SMBUS Master Mode
The DS125BR401 device supports reading directly from an external EEPROM device by implementing SMBus Master mode. When using the SMBus master mode, the DS125BR401 will read directly from specific location in the external EEPROM. When designing a system for using the external EEPROM, the user must follow these specific guidelines. For additional information, refer to SNLA228.
- Set ENSMB = Float — enable the SMBUS master mode.
- The external EEPROM device address byte must be 0xA0 and capable of 1-MHz operation at 2.5-V and 3.3-V supply.
- Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is 0xB0.
When tying multiple DS125BR401 devices to the SDA and SCL bus, use these guidelines to configure the devices.
- Use SMBus AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM. Example below is for four devices.
- U1: AD[3:0] = 0000 = 0xB0,
- U2: AD[3:0] = 0001 = 0xB2,
- U3: AD[3:0] = 0010 = 0xB4,
- U4: AD[3:0] = 0011 = 0xB6
- Use a pullup resistor on SDA and SCL; value = 2 kΩ
- Daisy-chain READ_EN (pin 26) and ALL_DONE (pin 27) from one device to the next device in the sequence so that they do not compete for the EEPROM at the same time.
- Tie READ_EN of the first device in the chain (U1) to GND
- Tie ALL_DONE of U1 to READ_EN of U2
- Tie ALL_DONE of U2 to READ_EN of U3
- Tie ALL_DONE of U3 to READ_EN of U4
- Optional: Tie ALL_DONE output of U4 to a LED to show the devices have been loaded successfully
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS125BR401 device. The first 3 bytes of the EEPROM always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled, a fixed pattern (8’hA5) is written/read instead of the CRC byte from the CRC location, to simplify the control. There is a MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS125BR401 address and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM. There are 37 bytes of data size for each DS125BR401 device. For additional information on EEPROM programming, refer to SNLA228.
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:2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5AD8
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
NOTE
The maximum EEPROM size supported is 8-kbits (1024 × 8 bits).
Table 7. EEPROM Register Map - Single Device With Default Value
| EEPROM Address Byte | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | BIt 0 | ||
|---|---|---|---|---|---|---|---|---|---|---|
| Description | 0x00 | CRC EN | Address Map Present | EEPROM > 256 Bytes | Reserved | DEVICE COUNT[3] | DEVICE COUNT[2] | DEVICE COUNT[1] | DEVICE COUNT[0] | |
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x01 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x02 | Max EEPROM Burst size[7] | Max EEPROM Burst size[6] | Max EEPROM Burst size[5] | Max EEPROM Burst size[4] | Max EEPROM Burst size[3] | Max EEPROM Burst size[2] | Max EEPROM Burst size[1] | Max EEPROM Burst size[0] | |
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x03 | PWDN_ch7 | PWDN_ch6 | PWDN_ch5 | PWDN_ch4 | PWDN_ch3 | PWDN_ch2 | PWDN_ch1 | PWDN_ch0 | |
| SMBus Register | 0x01 [7] | 0x01 [6] | 0x01 [5] | 0x01 [4] | 0x01 [3] | 0x01 [2] | 0x01 [1] | 0x01 [0] | ||
| Default Value | 0x00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x04 | lpbk_1 | lpbk_0 | PWDN_INPUTS | PWDN_OSC | Ovrd_PWDN | Reserved | Reserved | Reserved | |
| SMBus Register | 0x02 [5] | 0x02 [4] | 0x02 [3] | 0x02 [2] | 0x02 [0] | 0x04 [7] | 0x04 [6] | 0x04 [5] | ||
| Default Value | 00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x05 | Reserved | Reserved | Reserved | Reserved | Reserved | rxdet_btb_en | Ovrd_idle_th | Ovrd_RES | |
| SMBus Register | 0x04 [4] | 0x04 [3] | 0x04 [2] | 0x04 [1] | 0x04 [0] | 0x06 [4] | 0x08 [6] | 0x08 [5] | ||
| Default Value | 04 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | |
| Description | 0x06 | Ovrd_IDLE | Ovrd_RX_DET | Ovrd_MODE | Ovrd_RES | Ovrd_RES | rx_delay_sel_2 | rx_delay_sel_1 | rx_delay_sel_0 | |
| SMBus Register | 0x08 [4] | 0x08 [3] | 0x08 [2] | 0x08 [1] | 0x08 [0] | 0x0B [6] | 0x0B [5] | 0x0B [4] | ||
| Default Value | 07 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | |
| Description | 0x07 | RD_delay_sel_3 | RD_delay_sel_2 | RD_delay_sel_1 | RD_delay_sel_0 | ch0_Idle_auto | ch0_Idle_sel | ch0_RXDET_1 | ch0_RXDET_0 | |
| SMBus Register | 0x0B [3] | 0x0B [2] | 0x0B [1] | 0x0B [0] | 0x0E [5] | 0x0E [4] | 0x0E [3] | 0x0E [2] | ||
| Default Value | 00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x08 | ch0_BST_7 | ch0_BST_6 | ch0_BST_5 | ch0_BST_4 | ch0_BST_3 | ch0_BST_2 | ch0_BST_1 | ch0_BST_0 | |
| SMBus Register | 0x0F [7] | 0x0F [6] | 0x0F [5] | 0x0F [4] | 0x0F [3] | 0x0F [2] | 0x0F [1] | 0x0F [0] | ||
| Default Value | 2F | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | |
| Description | 0x09 | ch0_Sel_scp | ch0_Sel_mode | ch0_RES_2 | ch0_RES_1 | ch0_RES_0 | ch0_VOD_2 | ch0_VOD_1 | ch0_VOD_0 | |
| SMBus Register | 0x10 [7] | 0x10 [6] | 0x10 [5] | 0x10 [4] | 0x10 [3] | 0x10 [2] | 0x10 [1] | 0x10 [0] | ||
| Default Value | AD | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | |
| Description | 0x0A | ch0_DEM_2 | ch0_DEM_1 | ch0_DEM_0 | ch0_Slow | ch0_idle_tha_1 | ch0_idle_tha_0 | ch0_idle_thd_1 | ch0_idle_thd_0 | |
| SMBus Register | 0x11 [2] | 0x11 [1] | 0x11 [0] | 0x12 [7] | 0x12 [3] | 0x12 [2] | 0x12 [1] | 0x12 [0] | ||
| Default Value | 40 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x0B | ch1_Idle_auto | ch1_Idle_sel | ch1_RXDET_1 | ch1_RXDET_0 | ch1_BST_7 | ch1_BST_6 | ch1_BST_5 | ch1_BST_4 | |
| SMBus Register | 0x15 [5] | 0x15 [4] | 0x15 [3] | 0x15 [2] | 0x16 [7] | 0x16 [6] | 0x16 [5] | 0x16 [4] | ||
| Default Value | 02 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |
| Description | 0x0C | ch1_BST_3 | ch1_BST_2 | ch1_BST_1 | ch1_BST_0 | ch1_Sel_scp | ch1_Sel_mode | ch1_RES_2 | ch1_RES_1 | |
| SMBus Register | 0x16 [3] | 0x16 [2] | 0x16 [1] | 0x16 [0] | 0x17 [7] | 0x17 [6] | 0x17 [5] | 0x17 [4] | ||
| Default Value | FA | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | |
| Description | 0x0D | ch1_RES_0 | ch1_VOD_2 | ch1_VOD_1 | ch1_VOD_0 | ch1_DEM_2 | ch1_DEM_1 | ch1_DEM_0 | ch1_Slow | |
| SMBus Register | 0x17 [3] | 0x17 [2] | 0x17 [1] | 0x17 [0] | 0x18 [2] | 0x18 [1] | 0x18 [0] | 0x19 [7] | ||
| Default Value | 2F | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | |
| Description | 0x0E | ch1_idle_tha_1 | ch1_idle_tha_0 | ch1_idle_thd_1 | ch1_idle_thd_0 | ch2_Idle_auto | ch2_Idle_sel | ch2_RXDET_1 | ch2_RXDET_0 | |
| SMBus Register | 0x19 [3] | 0x19 [2] | 0x19 [1] | 0x19 [0] | 0x1C [5] | 0x1C [4] | 0x1C [3] | 0x1C [2] | ||
| Default Value | 00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x0F | ch2_BST_7 | ch2_BST_6 | ch2_BST_5 | ch2_BST_4 | ch2_BST_3 | ch2_BST_2 | ch2_BST_1 | ch2_BST_0 | |
| SMBus Register | 0x1D [7] | 0x1D [6] | 0x1D [5] | 0x1D [4] | 0x1D [3] | 0x1D [2] | 0x1D [1] | 0x1D [0] | ||
| Default Value | 2F | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | |
| Description | 0x10 | ch2_Sel_scp | ch2_Sel_mode | ch2_RES_2 | ch2_RES_1 | ch2_RES_0 | ch2_VOD_2 | ch2_VOD_1 | ch2_VOD_0 | |
| SMBus Register | 0x1E [7] | 0x1E [6] | 0x1E [5] | 0x1E [4] | 0x1E [3] | 0x1E [2] | 0x1E [1] | 0x1E [0] | ||
| Default Value | AD | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | |
| Description | 0x11 | ch2_DEM_2 | ch2_DEM_1 | ch2_DEM_0 | ch2_Slow | ch2_idle_tha_1 | ch2_idle_tha_0 | ch2_idle_thd_1 | ch2_idle_thd_0 | |
| SMBus Register | 0x1F [2] | 0x1F [1] | 0x1F [0] | 0x20 [7] | 0x20 [3] | 0x20 [2] | 0x20 [1] | 0x20 [0] | ||
| Default Value | 40 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x12 | ch3_Idle_auto | ch3_Idle_sel | ch3_RXDET_1 | ch3_RXDET_0 | ch3_BST_7 | ch3_BST_6 | ch3_BST_5 | ch3_BST_4 | |
| SMBus Register | 0x23 [5] | 0x23 [4] | 0x23 [3] | 0x23 [2] | 0x24 [7] | 0x24 [6] | 0x24 [5] | 0x24 [4] | ||
| Default Value | 02 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |
| Description | 0x13 | ch3_BST_3 | ch3_BST_2 | ch3_BST_1 | ch3_BST_0 | ch3_Sel_scp | ch3_Sel_mode | ch3_RES_2 | ch3_RES_1 | |
| SMBus Register | 0x24 [3] | 0x24 [2] | 0x24 [1] | 0x24 [0] | 0x25 [7] | 0x25 [6] | 0x25 [5] | 0x25 [4] | ||
| Default Value | FA | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | |
| Description | 0x14 | ch3_RES_0 | ch3_VOD_2 | ch3_VOD_1 | ch3_VOD_0 | ch3_DEM_2 | ch3_DEM_1 | ch3_DEM_0 | ch3_Slow | |
| SMBus Register | 0x25 [3] | 0x25 [2] | 0x25 [1] | 0x25 [0] | 0x26 [2] | 0x26 [1] | 0x26 [0] | 0x27 [7] | ||
| Default Value | D4 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | |
| Description | 0x15 | ch3_idle_tha_1 | ch3_idle_tha_0 | ch3_idle_thd_1 | ch3_idle_thd_0 | ovrd_fast_idle | en_high_idle_th_n | en_high_idle_th_s | en_fast_idle_n | |
| SMBus Register | 0x27 [3] | 0x27 [2] | 0x27 [1] | 0x27 [0] | 0x28 [6] | 0x28 [5] | 0x28 [4] | 0x28 [3] | ||
| Default Value | 09 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Description | 0x16 | en_fast_idle_s | eqsd_mgain_n | eqsd_mgain_s | ch4_Idle_auto | ch4_Idle_sel | ch4_RXDET_1 | ch4_RXDET_0 | ch4_BST_7 | |
| SMBus Register | 0x28 [2] | 0x28 [1] | 0x28 [0] | 0x2B [5] | 0x2B [4] | 0x2B [3] | 0x2B [2] | 0x2C [7] | ||
| Default Value | 80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x17 | ch4_BST_6 | ch4_BST_5 | ch4_BST_4 | ch4_BST_3 | ch4_BST_2 | ch4_BST_1 | ch4_BST_0 | ch4_Sel_scp | |
| SMBus Register | 0x2C [6] | 0x2C [5] | 0x2C [4] | 0x2C [3] | 0x2C [2] | 0x2C [1] | 0x2C [0] | 0x2D [7] | ||
| Default Value | 5F | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | |
| Description | 0x18 | ch4_Sel_mode | ch4_RES_2 | ch4_RES_1 | ch4_RES_0 | ch4_VOD_2 | ch4_VOD_1 | ch4_VOD_0 | ch4_DEM_2 | |
| SMBus Register | 0x2D [6] | 0x2D [5] | 0x2D [4] | 0x2D [3] | 0x2D [2] | 0x2D [1] | 0x2D [0] | 0x2E [2] | ||
| Default Value | 5A | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | |
| Description | 0x19 | ch4_DEM_1 | ch4_DEM_0 | ch4_Slow | ch4_idle_tha_1 | ch4_idle_tha_0 | ch4_idle_thd_1 | ch4_idle_thd_0 | ch5_Idle_auto | |
| SMBus Register | 0x2E [1] | 0x2E [0] | 0x2F [7] | 0x2F [3] | 0x2F [2] | 0x2F [1] | 0x2F [0] | 0x32 [5] | ||
| Default Value | 80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x1A | ch5_Idle_sel | ch5_RXDET_1 | ch5_RXDET_0 | ch5_BST_7 | ch5_BST_6 | ch5_BST_5 | ch5_BST_4 | ch5_BST_3 | |
| SMBus Register | 0x32 [4] | 0x32 [3] | 0x32 [2] | 0x33 [7] | 0x33 [6] | 0x33 [5] | 0x33 [4] | 0x33 [3] | ||
| Default Value | 05 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | |
| Description | 0x1B | ch5_BST_2 | ch5_BST_1 | ch5_BST_0 | ch5_Sel_scp | ch5_Sel_mode | ch5_RES_2 | ch5_RES_1 | ch5_RES_0 | |
| SMBus Register | 0x33 [2] | 0x33 [1] | 0x33 [0] | 0x34 [7] | 0x34 [6] | 0x34 [5] | 0x34 [4] | 0x34 [3] | ||
| Default Value | F5 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | |
| Description | 0x1C | ch5_VOD_2 | ch5_VOD_1 | ch5_VOD_0 | ch5_DEM_2 | ch5_DEM_1 | ch5_DEM_0 | ch5_Slow | ch5_idle_tha_1 | |
| SMBus Register | 0x34 [2] | 0x34 [1] | 0x34 [0] | 0x35 [2] | 0x35 [1] | 0x35 [0] | 0x36 [7] | 0x36 [3] | ||
| Default Value | A8 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | |
| Description | 0x1D | ch5_idle_tha_0 | ch5_idle_thd_1 | ch5_idle_thd_0 | ch6_Idle_auto | ch6_Idle_sel | ch6_RXDET_1 | ch6_RXDET_0 | ch6_BST_7 | |
| SMBus Register | 0x36 [2] | 0x36 [1] | 0x36 [0] | 0x39 [5] | 0x39 [4] | 0x39 [3] | 0x39 [2] | 0x3A [7] | ||
| Default Value | 00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x1E | ch6_BST_6 | ch6_BST_5 | ch6_BST_4 | ch6_BST_3 | ch6_BST_2 | ch6_BST_1 | ch6_BST_0 | ch6_Sel_scp | |
| SMBus Register | 0x3A [6] | 0x3A [5] | 0x3A [4] | 0x3A [3] | 0x3A [2] | 0x3A [1] | 0x3A [0] | 0x3B [7] | ||
| Default Value | 5F | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | |
| Description | 0x1F | ch6_Sel_mode | ch6_RES_2 | ch6_RES_1 | ch6_RES_0 | ch6_VOD_2 | ch6_VOD_1 | ch6_VOD_0 | ch6_DEM_2 | |
| SMBus Register | 0x3B [6] | 0x3B [5] | 0x3B [4] | 0x3B [3] | 0x3B [2] | 0x3B [1] | 0x3B [0] | 0x3C [2] | ||
| Default Value | 5A | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | |
| Description | 0x20 | ch6_DEM_1 | ch6_DEM_0 | ch6_Slow | ch6_idle_tha_1 | ch6_idle_tha_0 | ch6_idle_thd_1 | ch6_idle_thd_0 | ch7_Idle_auto | |
| SMBus Register | 0x3C [1] | 0x3C [0] | 0x3D [7] | 0x3D [3] | 0x3D [2] | 0x3D [1] | 0x3D [0] | 0x40 [5] | ||
| Default Value | 80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x21 | ch7_Idle_sel | ch7_RXDET_1 | ch7_RXDET_0 | ch7_BST_7 | ch7_BST_6 | ch7_BST_5 | ch7_BST_4 | ch7_BST_3 | |
| SMBus Register | 0x40 [4] | 0x40 [3] | 0x40 [2] | 0x41 [7] | 0x41 [6] | 0x41 [5] | 0x41 [4] | 0x41 [3] | ||
| Default Value | 05 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | |
| Description | 0x22 | ch7_BST_2 | ch7_BST_1 | ch7_BST_0 | ch7_Sel_scp | ch7_Sel_mode | ch7_RES_2 | ch7_RES_1 | ch7_RES_0 | |
| SMBus Register | 0x41 [2] | 0x41 [1] | 0x41 [0] | 0x42 [7] | 0x42 [6] | 0x42 [5] | 0x42 [4] | 0x42 [3] | ||
| Default Value | F5 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | |
| Description | 0x23 | ch7_VOD_2 | ch7_VOD_1 | ch7_VOD_0 | ch7_DEM_2 | ch7_DEM_1 | ch7_DEM_0 | ch7_Slow | ch7_idle_tha_1 | |
| SMBus Register | 0x42 [2] | 0x42 [1] | 0x42 [0] | 0x43 [2] | 0x43 [1] | 0x43 [0] | 0x44 [7] | 0x44 [3] | ||
| Default Value | A8 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | |
| Description | 0x24 | ch7_idle_tha_0 | ch7_idle_thd_1 | ch7_idle_thd_0 | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x44 [2] | 0x44 [1] | 0x44 [0] | 0x47 [3] | 0x47 [2] | 0x47 [2] | 0x47 [0] | 0x48 [7] | ||
| Default Value | 00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x25 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x48 [6] | 0x4C [7] | 0x4C [6] | 0x4C [5] | 0x4C [4] | 0x4C [3] | 0x4C [0] | 0x59 [0] | ||
| Default Value | 00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Description | 0x26 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x5A [7] | 0x5A [6] | 0x5A [5] | 0x5A [4] | 0x5A [3] | 0x5A [2] | 0x5A [1] | 0x5A [0] | ||
| Default Value | 54 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | |
| Description | 0x27 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | |
| SMBus Register | 0x5B [7] | 0x5B [6] | 0x5B [5] | 0x5B [4] | 0x5B [3] | 0x5B [2] | 0x5B [1] | 0x5B [0] | ||
| Default Value | 54 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | |
Table 8. Example of EEPROM for Four Devices Using Two Address Maps
| EEPROM Address | Address (Hex) | EEPROM Data | Comments |
|---|---|---|---|
| 0 | 00 | 0x43 | CRC_EN = 0, Address Map = 1, >256 bytes = 0, Device Count[3:0] = 3 |
| 1 | 01 | 0x00 | |
| 2 | 02 | 0x08 | EEPROM Burst Size |
| 3 | 03 | 0x00 | CRC not used |
| 4 | 04 | 0x0B | Device 0 Address Location |
| 5 | 05 | 0x00 | CRC not used |
| 6 | 06 | 0x0B | Device 1 Address Location |
| 7 | 07 | 0x00 | CRC not used |
| 8 | 08 | 0x30 | Device 2 Address Location |
| 9 | 09 | 0x00 | CRC not used |
| 10 | 0A | 0x30 | Device 3 Address Location |
| 11 | 0B | 0x00 | Begin Device 0, 1 - Address Offset 3 |
| 12 | 0C | 0x00 | |
| 13 | 0D | 0x04 | |
| 14 | 0E | 0x07 | |
| 15 | 0F | 0x00 | |
| 16 | 10 | 0x00 | EQ CHB0 = 00 |
| 17 | 11 | 0xAB | VOD CHB0 = 1 V |
| 18 | 12 | 0x00 | DEM CHB0 = 0 (0 dB) |
| 19 | 13 | 0x00 | EQ CHB1 = 00 |
| 20 | 14 | 0x0A | VOD CHB1 = 1 V |
| 21 | 15 | 0xB0 | DEM CHB1 = 0 (0 dB) |
| 22 | 16 | 0x00 | |
| 23 | 17 | 0x00 | EQ CHB2 = 00 |
| 24 | 18 | 0xAB | VOD CHB2 = 1 V |
| 25 | 19 | 0x00 | DEM CHB2 = 0 (0 dB) |
| 26 | 1A | 0x00 | EQ CHB3 = 00 |
| 27 | 1B | 0x0A | VOD CHB3 = 1 V |
| 28 | 1C | 0xB0 | DEM CHB3 = 0 (0 dB) |
| 29 | 1D | 0x01 | |
| 30 | 1E | 0x80 | |
| 31 | 1F | 0x01 | EQ CHA0 = 00 |
| 32 | 20 | 0x56 | VOD CHA0 = 1 V |
| 33 | 21 | 0x00 | DEM CHA0 = 0 (0 dB) |
| 34 | 22 | 0x00 | EQ CHA1 = 00 |
| 35 | 23 | 0x15 | VOD CHA1 = 1 V |
| 36 | 24 | 0x60 | DEM CHA1 = 0 (0 dB) |
| 37 | 25 | 0x00 | |
| 38 | 26 | 0x01 | EQ CHA2 = 00 |
| 39 | 27 | 0x56 | VOD CHA2 = 1 V |
| 40 | 28 | 0x00 | DEM CHA2 = 0 (0 dB) |
| 41 | 29 | 0x00 | EQ CHA3 = 00 |
| 42 | 2A | 0x15 | VOD CHA3 = 1 V |
| 43 | 2B | 0x60 | DEM CHA3 = 0 (0 dB) |
| 44 | 2C | 0x00 | |
| 45 | 2D | 0x00 | |
| 46 | 2E | 0x54 | |
| 47 | 2F | 0x54 | End Device 0, 1 - Address Offset 39 |
| 48 | 30 | 0x00 | Begin Device 2, 3 - Address Offset 3 |
| 49 | 31 | 0x00 | |
| 50 | 32 | 0x04 | |
| 51 | 33 | 0x07 | |
| 52 | 34 | 0x00 | |
| 53 | 35 | 0x00 | EQ CHB0 = 00 |
| 54 | 36 | 0xAB | VOD CHB0 = 1 V |
| 55 | 37 | 0x00 | DEM CHB0 = 0 (0 dB) |
| 56 | 38 | 0x00 | EQ CHB1 = 00 |
| 57 | 39 | 0x0A | VOD CHB1 = 1 V |
| 58 | 3A | 0xB0 | DEM CHB1 = 0 (0 dB) |
| 59 | 3B | 0x00 | |
| 60 | 3C | 0x00 | EQ CHB2 = 00 |
| 61 | 3D | 0xAB | VOD CHB2 = 1 V |
| 62 | 3E | 0x00 | DEM CHB2 = 0 (0 dB) |
| 63 | 3F | 0x00 | EQ CHB3 = 00 |
| 64 | 40 | 0x0A | VOD CHB3 = 1 V |
| 65 | 41 | 0xB0 | DEM CHB3 = 0 (0 dB) |
| 66 | 42 | 0x01 | |
| 67 | 43 | 0x80 | |
| 68 | 44 | 0x01 | EQ CHA0 = 00 |
| 69 | 45 | 0x56 | VOD CHA0 = 1 V |
| 70 | 46 | 0x00 | DEM CHA0 = 0 (0 dB) |
| 71 | 47 | 0x00 | EQ CHA1 = 00 |
| 72 | 48 | 0x15 | VOD CHA1 = 1 V |
| 73 | 49 | 0x60 | DEM CHA1 = 0 (0 dB) |
| 74 | 4A | 0x00 | |
| 75 | 4B | 0x01 | EQ CHA2 = 00 |
| 76 | 4C | 0x56 | VOD CHA2 = 1 V |
| 77 | 4D | 0x00 | DEM CHA2 = 0 (0 dB) |
| 78 | 4E | 0x00 | EQ CHA3 = 00 |
| 79 | 4F | 0x15 | VOD CHA3 = 1 V |
| 80 | 50 | 0x60 | DEM CHA3 = 0 (0 dB) |
| 81 | 51 | 0x00 | |
| 82 | 52 | 0x00 | |
| 83 | 53 | 0x54 | |
| 84 | 54 | 0x54 | End Device 2, 3 - Address Offset 39 |
Note: CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. This example has all eight channels set to EQ = 00 (min boost), VOD = 1 V, DEM = 0 (0 dB) and multiple device can point to the same address map. Maximum EEPROM size is 8Kb (1024 × 8 bits).
9.5.3 System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1 kΩ to VDD to enable SMBus slave mode and allow access to the configuration registers.
The DS125BR401 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address inputs. The AD[3:0] pins have internal pulldown. When left floating or pulled low the AD[3:0] = 0000'b, the device default address byte is 0xB0. Based on the SMBus 2.0 specification, the DS125BR401 has a 7-bit slave address. The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the AD[3:0] inputs. Table 9 shows the 16 addresses.
Table 9. Device Slave Address Bytes
| AD[3:0] Settings | Address Bytes (HEX) |
|---|---|
| 0000 | B0 |
| 0001 | B2 |
| 0010 | B4 |
| 0011 | B6 |
| 0100 | B8 |
| 0101 | BA |
| 0110 | BC |
| 0111 | BE |
| 1000 | C0 |
| 1001 | C2 |
| 1010 | C4 |
| 1011 | C6 |
| 1100 | C8 |
| 1101 | CA |
| 1110 | CC |
| 1111 | CE |
The SDA, SCL pins are 3.3-V tolerant, but are not 5-V tolerant. External pullup resistor is required on the SDA. The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also require an external pullup resistor and it depends on the Host that drives the bus.
9.5.3.1 Transfer of Data Through the SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
9.5.3.2 SMBus Transactions
The device supports WRITE and READ transactions. See Table 10 for register address, type (Read/Write, Read Only), default value and function information.
9.5.3.3 Writing a Register
To write a register, the following protocol is used (see SMBus 2.0 specification).
- The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
- The Device (Slave) drives the ACK bit (“0”).
- The Host drives the 8-bit Register Address.
- The Device drives an ACK bit (“0”).
- The Host drive the 8-bit data byte.
- The Device drives an ACK bit (“0”).
- The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur.
9.5.3.4 Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
- The Host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
- The Device (Slave) drives the ACK bit (0).
- The Host drives the 8-bit Register Address.
- The Device drives an ACK bit (0).
- The Host drives a START condition.
- The Host drives the 7-bit SMBus Address, and a 1 indicating a READ.
- The Device drives an ACK bit 0.
- The Device drives the 8-bit data value (register contents).
- The Host drives a NACK bit 1 indicating end of the READ transfer.
- The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur.
See Table 10 for more information.
9.6 Register Maps
Table 10. SMBUS Slave Mode Register Map
| Address | Register Name | Bit | Field | Type | Default | EEPROM Bit | Description |
|---|---|---|---|---|---|---|---|
| 0x00 | Device Address Observation | 7 | Reserved | R/W | 0x00 | Set bit to 0. | |
| 6:3 | Address Bit AD[3:0] |
R | Observation of AD[3:0] bits [6]: AD3 [5]: AD2 [4]: AD1 [3]: AD0 |
||||
| 2 | EEPROM Read Done | R | 1: Device completed the read from external EEPROM. | ||||
| 1:0 | Reserved | R/W | Set bits to 0. | ||||
| 0x01 | PWDN Channels | 7:0 | PWDN CHx | R/W | 0x00 | Yes | Power Down per Channel [7]: CH7 – CHA_3 [6]: CH6 – CHA_2 [5]: CH5 – CHA_1 [4]: CH4 – CHA_0 [3]: CH3 – CHB_3 [2]: CH2 – CHB_2 [1]: CH1 – CHB_1 [0]: CH0 – CHB_0 0x00 = all channels enabled 0xFF = all channels disabled Note: override PWDN pin. |
| 0x02 | Override PWDN, LPBK Control |
7:6 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 5:4 | LPBK Control |
Yes | 00: Use LPBK pin control 01: INA_n to OUTB_n loopback 10: INB_n to OUTA_n loopback 11: Disable loopback and ignore LPBK pin. |
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| 3:1 | Reserved | Set bits to 0. | |||||
| 0 | Override PWDN pin |
Yes | 1: Block PWDN pin control 0: Allow PWDN pin control |
||||
| 0x03 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x04 | Reserved | 7:0 | Reserved | R/W | 0x00 | Yes | Set bits to 0 |
| 0x05 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x05 | Reserved | 7:0 | Reserved | R/W | 0x00 | Reserved | |
| 0x06 | Slave Register Control | 7:5 | Reserved | R/W | 0x10 | Set bits to 0. | |
| 4 | Reserved | Yes | Set bit to 1. | ||||
| 3 | Register Enable | 1 = Enable SMBus Register Control 0 = Disable SMBus Register Control Note: In order to change VOD, DEM, and EQ of the channels in slave mode, this bit must be set to 1. |
|||||
| 0x07 | Digital Reset and Control | 7 | Reserved | R/W | 0x01 | Set bit to 0. | |
| 6 | Reset Registers | Self clearing bit, set to 1 to reset the register to default values | |||||
| 5 | Reset SMBus Master | Self clearing reset to SMBus master state machine | |||||
| 4:0 | Reserved | Set bits to 0 0001'b. | |||||
| 0x08 | Override Pin Control |
7 | Reserved | R/W | 0x00 | Set bit to 0. | |
| 6 | Override SD_TH | Yes | 1: Block SD_TH pin control 0: Allow SD_TH pin control |
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| 5 | Reserved | Yes | Set bit to 0. | ||||
| 4 | Override IDLE | Yes | 1: IDLE control by registers 0: IDLE control by signal detect |
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| 3 | Override RXDET | Yes | 1: Block RXDET pin control 0: Allow RXDET pin control |
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| 2 | Override MODE | Yes | 1: Block MODE pin control 0: Allow MODE pin control |
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| 1 | Reserved | Set bit to 0. | |||||
| 0 | Reserved | Set bit to 0. | |||||
| 0x09 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x0A | Signal Detect Monitor | 7:0 | SD_TH Status | R | 0x00 | CH7 - CH0 Internal Signal Detector Indicator [7]: CH7 - CHA_3 [6]: CH6 - CHA_2 [5]: CH5 - CHA_1 [4]: CH4 - CHA_0 [3]: CH3 - CHB_3 [2]: CH2 - CHB_2 [1]: CH1 - CHB_1 [0]: CH0 - CHB_0 0 = Signal detected at input (active data) 1 = Signal not detected at input (idle state) NOTE: These bits only function when RATE pin = FLOAT |
|
| 0x0B | Reserved | 7 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 6:0 | Reserved | R/W | 0x70 | Yes | Set bits to 111 0000'b | ||
| 0x0C | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x0D | CH0 - CHB0 Signal Detect |
7:3 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 2 | SD Reset | 1: Force signal detect "off" 0: Normal operation |
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| 1 | SD Preset | 1: Force signal detect "on" 0: Normal operation |
|||||
| 0 | Reserved | Set bit to 0. | |||||
| 0x0E | CH0 - CHB0 IDLE, RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 5 | IDLE_AUTO | Yes | 1 = Allow IDLE_SEL control in bit 4 0 = Automatic IDLE detect Note: override IDLE control. |
||||
| 4 | IDLE_SEL | Yes | 1: Output is MUTED (electrical idle) 0: Output is ON Note: override IDLE control. |
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| 3:2 | RXDET | Yes | 00: Input is hi-z impedance 01: Auto RX-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-z until detection; once detected input termination is 50 Ω 10: Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is hi-z until detection; once detected input termination is 50 Ω 11: Input is 50 Ω Note: override RXDET pin. |
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| 1:0 | Reserved | Set bits to 0. | |||||
| 0x0F | CH0 - CHB0 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | IB0 EQ Control - total of 256 levels. See Table 2. |
| 0x10 | CH0 - CHB0 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1: Enable the short circuit protection 0: Disable the short circuit protection |
| 6 | MODE_SEL | Yes | 1: PCIe Gen-1 or PCIe Gen-2 0: PCIe Gen-3 Note: override the MODE pin. |
||||
| 5:3 | Reserved | Yes | Set bits to default value - 101. | ||||
| 2:0 | VOD Control | Yes | OB0 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.9 V 011: 1 V 100: 1.1 V 101: 1.2 V (default) 110: 1.3 V 111: 1.4 V |
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| 0x11 | CH0 - CHB0 DEM |
7 | RXDET STATUS | R | 0x02 | Observation bit for RXDET CH0 - CHB0. 1: RX = detected 0: RX = not detected |
|
| 6:5 | MODE_DET STATUS | R | Observation bit for MODE_DET CH0 - CHB0. 00: PCIe Gen-1 (2.5G) 01: PCIe Gen-2 (5G) 11: PCIe Gen-3 (8G+) Note: Only functions when MODE Pin = Automatic |
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| 4:3 | Reserved | R/W | Set bits to 0. | ||||
| 2:0 | DEM Control | R/W | Yes | OB0 DEM Control 000: 0 dB 001: –1.5 dB 010: –3.5 dB (default) 011: –5 dB 100: –6 dB 101: –8 dB 110: –9 dB 111: –12 dB |
|||
| 0x12 | CH0 - CHB0 IDLE Threshold |
7:4 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 3:2 | IDLE tha | Yes | Assert threshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note: override the SD_TH pin. |
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| 1:0 | IDLE thd | Yes | Deassert threshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note: override the SD_TH pin. |
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| 0x13 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x14 | CH1 - CHB1 Signal Detect |
7:3 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 2 | SD Reset | 1: Force signal detect "off" 0: Normal operation |
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| 1 | SD Preset | 1: Force signal detect "on" 0: Normal operation |
|||||
| 0 | Reserved | Set bit to 0. | |||||
| 0x15 | CH1 - CHB1 IDLE, RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 5 | IDLE_AUTO | Yes | 1 = Allow IDLE_SEL control in bit 4 0 = Automatic IDLE detect Note: override IDLE control. |
||||
| 4 | IDLE_SEL | Yes | 1: Output is MUTED (electrical idle) 0: Output is ON Note: override IDLE control. |
||||
| 3:2 | RXDET | Yes | 00: Input is hi-z impedance 01: Auto RX-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-z until detection; once detected input termination is 50 Ω 10: Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is high-z until detection; once detected input termination is 50 Ω 11: Input is 50 Ω Note: override RXDET pin. |
||||
| 1:0 | Reserved | Set bits to 0. | |||||
| 0x16 | CH1 - CHB1 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | IB1 EQ Control - total of 256 levels. See Table 2. |
| 0x17 | CH1 - CHB1 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1: Enable the short circuit protection 0: Disable the short circuit protection |
| 6 | MODE_SEL | Yes | 1: PCIe Gen-1 or PCIe Gen-2 0: PCIe Gen-3 Note: override the MODE pin. |
||||
| 5:3 | Reserved | Yes | Set bits to default value - 101. | ||||
| 2:0 | VOD Control | Yes | OB1 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.9 V 011: 1 V 100: 1.1 V 101: 1.2 V (default) 110: 1.3 V 111: 1.4 V |
||||
| 0x18 | CH1 - CHB1 DEM |
7 | RXDET STATUS | R | 0x02 | Observation bit for RXDET CH1 - CHB1. 1: RX = detected 0: RX = not detected |
|
| 6:5 | MODE_DET STATUS | R | Observation bit for MODE_DET CH1 - CHB1. 00: PCIe Gen-1 (2.5G) 01: PCIe Gen-2 (5G) 11: PCIe Gen-3 (8G+) Note: Only functions when MODE Pin = Automatic |
||||
| 4:3 | Reserved | R/W | Set bits to 0. | ||||
| 2:0 | DEM Control | R/W | Yes | OB1 DEM Control 000: 0 dB 001: –1.5 dB 010: –3.5 dB (default) 011: –5 dB 100: –6 dB 101: –8 dB 110: –9 dB 111: –12 dB |
|||
| 0x19 | CH1 - CHB1 IDLE Threshold |
7:4 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 3:2 | IDLE tha | Yes | Assert threshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note: override the SD_TH pin. |
||||
| 1:0 | IDLE thd | Yes | Deassert threshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note: override the SD_TH pin. |
||||
| 0x1A | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x1B | CH2 - CHB2 Signal Detect |
7:3 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 2 | SD Reset | 1: Force signal detect "off" 0: Normal operation |
|||||
| 1 | SD Preset | 1: Force signal detect "on" 0: Normal operation |
|||||
| 0 | Reserved | Set bit to 0. | |||||
| 0x1C | CH2 - CHB2 IDLE, RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 5 | IDLE_AUTO | Yes | 1 = Allow IDLE_SEL control in bit 4 0 = Automatic IDLE detect Note: override IDLE control. |
||||
| 4 | IDLE_SEL | Yes | 1: Output is MUTED (electrical idle) 0: Output is ON Note: override IDLE control. |
||||
| 3:2 | RXDET | Yes | 00: Input is hi-z impedance 01: Auto RX-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-z until detection; once detected input termination is 50 Ω 10: Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is hi-z until detection; once detected input termination is 50 Ω 11: Input is 50 Ω Note: override RXDET pin. |
||||
| 1:0 | Reserved | Set bits to 0. | |||||
| 0x1D | CH2 - CHB2 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | IB2 EQ Control - total of 256 levels. See Table 2. |
| 0x1E | CH2 - CHB2 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1: Enable the short circuit protection 0: Disable the short circuit protection |
| 6 | MODE_SEL | Yes | 1: PCIe Gen-1 or PCIe Gen-2 0: PCIe Gen-3 Note: override the MODE pin. |
||||
| 5:3 | Reserved | Yes | Set bits to default value - 101. | ||||
| 2:0 | VOD Control | Yes | OB2 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.9 V 011: 1 V 100: 1.1 V 101: 1.2 V (default) 110: 1.3 V 111: 1.4 V |
||||
| 0x1F | CH2 - CHB2 DEM |
7 | RXDET STATUS | R | 0x02 | Observation bit for RXDET CH2 - CHB2. 1: RX = detected 0: RX = not detected |
|
| 6:5 | MODE_DET STATUS | R | Observation bit for MODE_DET CH2 - CHB2. 00: PCIe Gen-1 (2.5 G) 01: PCIe Gen-2 (5 G) 11: PCIe Gen-3 (8 G+) Note: Only functions when MODE Pin = Automatic |
||||
| 4:3 | Reserved | R/W | Set bits to 0. | ||||
| 2:0 | DEM Control | R/W | Yes | OB2 DEM Control 000: 0 dB 001: –1.5 dB 010: –3.5 dB (default) 011: –5 dB 100: –6 dB 101: –8 dB 110: –9 dB 111: –12 dB |
|||
| 0x20 | CH2 - CHB2 IDLE Threshold |
7:4 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 3:2 | IDLE tha | Yes | Assert threshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note: override the SD_TH pin. |
||||
| 1:0 | IDLE thd | Yes | Deassert threshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note: override the SD_TH pin. |
||||
| 0x21 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x22 | CH3 - CHB3 Signal Detect |
7:3 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 2 | SD Reset | 1: Force signal detect "off" 0: Normal operation |
|||||
| 1 | SD Preset | 1: Force signal detect "on" 0: Normal operation |
|||||
| 0 | Reserved | Set bit to 0. | |||||
| 0x23 | CH3 - CHB3 IDLE, RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 5 | IDLE_AUTO | Yes | 1 = Allow IDLE_SEL control in bit 4 0 = Automatic IDLE detect Note: override IDLE control. |
||||
| 4 | IDLE_SEL | Yes | 1: Output is MUTED (electrical idle) 0: Output is ON Note: override IDLE control. |
||||
| 3:2 | RXDET | Yes | 00: Input is hi-z impedance 01: Auto RX-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-z until detection; once detected input termination is 50 Ω 10: Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is hi-z until detection; once detected input termination is 50 Ω 11: Input is 50 Ω Note: override RXDET pin. |
||||
| 1:0 | Reserved | Set bits to 0. | |||||
| 0x24 | CH3 - CHB3 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | IB3 EQ Control - total of 256 levels. See Table 2. |
| 0x25 | CH3 - CHB3 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1: Enable the short circuit protection 0: Disable the short circuit protection |
| 6 | MODE_SEL | Yes | 1: PCIe Gen-1 or PCIe Gen-2 0: PCIe Gen-3 Note: override the MODE pin. |
||||
| 5:3 | Reserved | Yes | Set bits to default value - 101. | ||||
| 2:0 | VOD Control | Yes | OB0 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.9 V 011: 1 V 100: 1.1 V 101: 1.2 V (default) 110: 1.3 V 111: 1.4 V |
||||
| 0x26 | CH3 - CHB3 DEM |
7 | RXDET STATUS | R | 0x02 | Observation bit for RXDET CH3 - CHB3. 1: RX = detected 0: RX = not detected |
|
| 6:5 | MODE_DET STATUS | R | Observation bit for MODE_DET CH3 - CHB3. 00: PCIe Gen-1 (2.5G) 01: PCIe Gen-2 (5G) 11: PCIe Gen-3 (8G+) Note: Only functions when MODE Pin = Automatic |
||||
| 4:3 | Reserved | R/W | Set bits to 0. | ||||
| 2:0 | DEM Control | R/W | Yes | OB3 DEM Control 000: 0 dB 001: –1.5 dB 010: –3.5 dB (default) 011: –5 dB 100: –6 dB 101: –8 dB 110: –9 dB 111: –12 dB |
|||
| 0x27 | CH3 - CHB3 IDLE Threshold |
7:4 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 3:2 | IDLE tha | Yes | Assert threshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note: override the SD_TH pin. |
||||
| 1:0 | IDLE thd | Yes | Deassert threshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note: override the SD_TH pin. |
||||
| 0x28 | Signal Detect Control | 7:6 | Reserved | R/W | 0x0C | Set bits to 0. | |
| 5:4 | High IDLE | Yes | Enable higher range of Signal Detect Thresholds [5]: CH0 - CH3 [4]: CH4 -CH7 |
||||
| 3:2 | Fast IDLE | Yes | Enable Fast OOB response [3]: CH0 - CH3 [2]: CH4 -CH7 |
||||
| 1:0 | Reduced SD Gain | Yes | Enable reduced Signal Detect Gain [1]: CH0 - CH3 [0]: CH4 -CH7 |
||||
| 0x29 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x2A | CH4 - CHA0 Signal Detect |
7:3 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 2 | SD Reset | 1: Force signal detect "off" 0: Normal operation |
|||||
| 1 | SD Preset | 1: Force signal detect "on" 0: Normal operation |
|||||
| 0 | Reserved | Set bit to 0. | |||||
| 0x2B | CH4 - CHA0 IDLE, RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 5 | IDLE_AUTO | Yes | 1 = Allow IDLE_SEL control in bit 4 0 = Automatic IDLE detect Note: override IDLE control. |
||||
| 4 | IDLE_SEL | Yes | 1: Output is MUTED (electrical idle) 0: Output is ON Note: override IDLE control. |
||||
| 3:2 | RXDET | Yes | 00: Input is hi-z impedance 01: Auto RX-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-z until detection; once detected input termination is 50 Ω 10: Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is hi-z until detection; once detected input termination is 50 Ω 11: Input is 50 Ω Note: override RXDET pin. |
||||
| 1:0 | Reserved | Set bits to 0. | |||||
| 0x2C | CH4 - CHA0 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | IA0 EQ Control - total of 256 levels. See Table 2. |
| 0x2D | CH4 - CHA0 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1: Enable the short circuit protection 0: Disable the short circuit protection |
| 6 | MODE_SEL | Yes | 1: PCIe Gen-1 or PCIe Gen-2 0: PCIe Gen-3 Note: override the MODE pin. |
||||
| 5:3 | Reserved | Yes | Set bits to default value - 101. | ||||
| 2:0 | VOD Control | Yes | OA0 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.9 V 011: 1 V 100: 1.1 V 101: 1.2 V (default) 110: 1.3 V 111: 1.4 V |
||||
| 0x2E | CH4 - CHA0 DEM |
7 | RXDET STATUS | R | 0x02 | Observation bit for RXDET CH4 - CHA0. 1: RX = detected 0: RX = not detected |
|
| 6:5 | MODE_DET STATUS | R | Observation bit for MODE_DET CH4 - CHA0. 00: PCIe Gen-1 (2.5G) 01: PCIe Gen-2 (5G) 11: PCIe Gen-3 (8G+) Note: Only functions when MODE Pin = Automatic |
||||
| 4:3 | Reserved | R/W | Set bits to 0. | ||||
| 2:0 | DEM Control | R/W | Yes | OA0 DEM Control 000: 0 dB 001: –1.5 dB 010: –3.5 dB (default) 011: –5 dB 100: –6 dB 101: –8 dB 110: –9 dB 111: –12 dB |
|||
| 0x2F | CH4 - CHA0 IDLE Threshold |
7:4 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 3:2 | IDLE tha | Yes | Assert threshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note: override the SD_TH pin. |
||||
| 1:0 | IDLE thd | Yes | Deassert threshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note: override the SD_TH pin. |
||||
| 0x30 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x31 | CH5 - CHA1 Signal Detect |
7:3 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 2 | SD Reset | 1: Force signal detect "off" 0: Normal operation |
|||||
| 1 | SD Preset | 1: Force signal detect "on" 0: Normal operation |
|||||
| 0 | Reserved | Set bit to 0. | |||||
| 0x32 | CH5 - CHA1 IDLE, RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 5 | IDLE_AUTO | Yes | 1 = Allow IDLE_SEL control in bit 4 0 = Automatic IDLE detect Note: override IDLE control. |
||||
| 4 | IDLE_SEL | Yes | 1: Output is MUTED (electrical idle) 0: Output is ON Note: override IDLE control. |
||||
| 3:2 | RXDET | Yes | 00: Input is hi-z impedance 01: Auto RX-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-z until detection; once detected input termination is 50 Ω 10: Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is hi-z until detection; once detected input termination is 50 Ω 11: Input is 50 Ω Note: override RXDET pin. |
||||
| 1:0 | Reserved | Set bits to 0. | |||||
| 0x33 | CH5 - CHA1 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | IA1 EQ Control - total of 256 levels. See Table 2. |
| 0x34 | CH5 - CHA1 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1: Enable the short circuit protection 0: Disable the short circuit protection |
| 6 | MODE_SEL | Yes | 1: PCIe Gen-1 or PCIe Gen-2 0: PCIe Gen-3 Note: override the MODE pin. |
||||
| 5:3 | Reserved | Yes | Set bits to default value - 101. | ||||
| 2:0 | VOD Control | Yes | OA1 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.9 V 011: 1 V 100: 1.1 V 101: 1.2 V (default) 110: 1.3 V 111: 1.4 V |
||||
| 0x35 | CH5 - CHA1 DEM |
7 | RXDET STATUS | R | 0x02 | Observation bit for RXDET CH5 - CHA1. 1: RX = detected 0: RX = not detected |
|
| 6:5 | MODE_DET STATUS | R | Observation bit for MODE_DET CH5 - CHA1. 00: PCIe Gen-1 (2.5G) 01: PCIe Gen-2 (5G) 11: PCIe Gen-3 (8G+) Note: Only functions when MODE Pin = Automatic |
||||
| 4:3 | Reserved | R/W | Set bits to 0. | ||||
| 2:0 | DEM Control | R/W | Yes | OA1 DEM Control 000: 0 dB 001: –1.5 dB 010: –3.5 dB (default) 011: –5 dB 100: –6 dB 101: –8 dB 110: –9 dB 111: –12 dB |
|||
| 0x36 | CH5 - CHA1 IDLE Threshold |
7:4 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 3:2 | IDLE tha | Yes | Assert threshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note: override the SD_TH pin. |
||||
| 1:0 | IDLE thd | Yes | Deassert threshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note: override the SD_TH pin. |
||||
| 0x37 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x38 | CH6 - CHA2 Signal Detect |
7:3 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 2 | SD Reset | 1: Force signal detect "off" 0: Normal operation |
|||||
| 1 | SD Preset | 1: Force signal detect "on" 0: Normal operation |
|||||
| 0 | Reserved | Set bit to 0. | |||||
| 0x39 | CH6 - CHA2 IDLE, RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 5 | IDLE_AUTO | Yes | 1 = Allow IDLE_SEL control in bit 4 0 = Automatic IDLE detect Note: override IDLE control. |
||||
| 4 | IDLE_SEL | Yes | 1: Output is MUTED (electrical idle) 0: Output is ON Note: override IDLE control. |
||||
| 3:2 | RXDET | Yes | 00: Input is hi-z impedance 01: Auto RX-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-z until detection; once detected input termination is 50 Ω 10: Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is hi-z until detection; once detected input termination is 50 Ω 11: Input is 50 Ω Note: override RXDET pin. |
||||
| 1:0 | Reserved | Set bits to 0. | |||||
| 0x3A | CH6 - CHA2 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | IA2 EQ Control - total of 256 levels. See Table 2. |
| 0x3B | CH6 - CHA2 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1: Enable the short circuit protection 0: Disable the short circuit protection |
| 6 | MODE_SEL | Yes | 1: PCIe Gen-1 or PCIe Gen-2 0: PCIe Gen-3 Note: override the MODE pin. |
||||
| 5:3 | Reserved | Yes | Set bits to default value - 101. | ||||
| 2:0 | VOD Control | Yes | OA2 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.9 V 011: 1 V 100: 1.1 V 101: 1.2 V (default) 110: 1.3 V 111: 1.4 V |
||||
| 0x3C | CH6 - CHA2 DEM |
7 | RXDET STATUS | R | 0x02 | Observation bit for RXDET CH6 - CHA2. 1: RX = detected 0: RX = not detected |
|
| 6:5 | MODE_DET STATUS | R | Observation bit for MODE_DET CH6 - CHA2. 00: PCIe Gen-1 (2.5G) 01: PCIe Gen-2 (5G) 11: PCIe Gen-3 (8G+) Note: Only functions when MODE Pin = Automatic |
||||
| 4:3 | Reserved | R/W | Set bits to 0. | ||||
| 2:0 | DEM Control | R/W | Yes | OA2 DEM Control 000: 0 dB 001: –1.5 dB 010: –3.5 dB (default) 011: –5 dB 100: –6 dB 101: –8 dB 110: –9 dB 111: –12 dB |
|||
| 0x3D | CH6 - CHA2 IDLE Threshold |
7:4 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 3:2 | IDLE tha | Yes | Assert threshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note: override the SD_TH pin. |
||||
| 1:0 | IDLE thd | Yes | Deassert threshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note: override the SD_TH pin. |
||||
| 0x3E | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x3F | CH7 - CHA3 Signal Detect |
7:3 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 2 | SD Reset | 1: Force signal detect "off" 0: Normal operation |
|||||
| 1 | SD Preset | 1: Force signal detect "on" 0: Normal operation |
|||||
| 0 | Reserved | Set bit to 0. | |||||
| 0x40 | CH7 - CHA3 IDLE, RXDET |
7:6 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 5 | IDLE_AUTO | Yes | 1 = Allow IDLE_SEL control in bit 4 0 = Automatic IDLE detect Note: override IDLE control. |
||||
| 4 | IDLE_SEL | Yes | 1: Output is MUTED (electrical idle) 0: Output is ON Note: override IDLE control. |
||||
| 3:2 | RXDET | Yes | 00: Input is hi-z impedance 01: Auto RX-Detect, outputs test every 12 ms for 600 ms (50 times) then stops; termination is hi-z until detection; once detected input termination is 50 Ω 10: Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is hi-z until detection; once detected input termination is 50 Ω 11: Input is 50 Ω Note: override RXDET pin. |
||||
| 1:0 | Reserved | Set bits to 0. | |||||
| 0x41 | CH7 - CHA3 EQ |
7:0 | EQ Control | R/W | 0x2F | Yes | IA3 EQ Control - total of 256 levels. See Table 2. |
| 0x42 | CH7 - CHA3 VOD |
7 | Short Circuit Protection | R/W | 0xAD | Yes | 1: Enable the short circuit protection 0: Disable the short circuit protection |
| 6 | MODE_SEL | Yes | 1: PCIe Gen-1 or PCIe Gen-2 0: PCIe Gen-3 Note: override the MODE pin. |
||||
| 5:3 | Reserved | Yes | Set bits to default value - 101. | ||||
| 2:0 | VOD Control | Yes | OA3 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.9 V 011: 1 V 100: 1.1 V 101: 1.2 V (default) 110: 1.3 V 111: 1.4 V |
||||
| 0x43 | CH7 - CHA3 DEM |
7 | RXDET STATUS | R | 0x02 | Observation bit for RXDET CH7 - CHA3. 1: RX = detected 0: RX = not detected |
|
| 6:5 | MODE_DET STATUS | R | Observation bit for MODE_DET CH7 - CHA3. 00: PCIe Gen-1 (2.5G) 01: PCIe Gen-2 (5G) 11: PCIe Gen-3 (8G+) Note: Only functions when MODE Pin = Automatic |
||||
| 4:3 | Reserved | R/W | Set bits to 0. | ||||
| 2:0 | DEM Control | R/W | Yes | OA3 DEM Control 000: 0 dB 001: –1.5 dB 010: –3.5 dB (default) 011: –5 dB 100: –6 dB 101: –8 dB 110: –9 dB 111: –12 dB |
|||
| 0x44 | CH7 - CHA3 IDLE Threshold |
7:4 | Reserved | R/W | 0x00 | Set bits to 0. | |
| 3:2 | IDLE tha | Yes | Assert threshold 00 = 180 mVp-p (default) 01 = 160 mVp-p 10 = 210 mVp-p 11 = 190 mVp-p Note: override the SD_TH pin. |
||||
| 1:0 | IDLE thd | Yes | Deassert threshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note: override the SD_TH pin. |
||||
| 0x45 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x46 | Reserved | 7:0 | Reserved | R/W | 0x38 | Set bits to 0x38 | |
| 0x47 | Reserved | 7:4 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 3:0 | Reserved | R/W | Yes | Set bits to 0 | |||
| 0x48 | Reserved | 7:6 | Reserved | R/W | 0x05 | Yes | Set bits to 0 |
| 5:0 | Reserved | R/W | Set bits to 00 0101'b | ||||
| 0x49 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x4A | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x4B | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x4C | Reserved | 7:3 | Reserved | R/W | 0x00 | Yes | Set bits to 0 |
| 2:1 | Reserved | R/W | Set bits to 0 | ||||
| 0 | Reserved | R/W | Yes | Set bits to 0 | |||
| 0x4D | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x4E | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x4F | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x50 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x51 | Device ID | 7:5 | VERSION | R | 0x44 | 010'b | |
| 4:0 | ID | 00100'b | |||||
| 0x52 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x53 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x54 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x55 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x56 | Reserved | 7:0 | Reserved | R/W | 0x10 | Set bits to 0x10 | |
| 0x57 | Reserved | 7:0 | Reserved | R/W | 0x64 | Set bits to 0x64 | |
| 0x58 | Reserved | 7:0 | Reserved | R/W | 0x21 | Set bits to 0x21 | |
| 0x59 | Reserved | 7:1 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0 | Reserved | Yes | Set bit to 0 | ||||
| 0x5A | Reserved | 7:0 | Reserved | R/W | 0x54 | Yes | Set bits to 0x54 |
| 0x5B | Reserved | 7:0 | Reserved | R/W | 0x54 | Yes | Set bits to 0x54 |
| 0x5C | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x5D | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x5E | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x5F | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x60 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 | |
| 0x61 | Reserved | 7:0 | Reserved | R/W | 0x00 | Set bits to 0 |