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ZHCSBO8A September 2013 – March 2014 DS125BR401A

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NJY|54
- MPQS027A

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6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

	MIN	MAX	UNIT
Supply Voltage (VDD - 2.5V)	-0.5	+2.75	V
Supply Voltage (VIN - 3.3V)	-0.5	+4.0	V
LVCMOS Input/Output Voltage	-0.5	+4.0	V
CML Input Voltage		-0.5V to (VDD+0.5)
CML Input Current	-30	+30	mA

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only.

6.2 Handling Ratings

		MIN	MAX	UNIT
ESD_HBM	HBM, STD - JESD22-A114F		4	kV
ESD_CDM	CDM, STD - JESD22-C101-D		1	kV
T_stg	Storage Temperature Range	-40	125	°C
T_solder	Lead Temperature Range Soldering (4 sec.) ⁽¹⁾		260	°C

(1) For soldering specifications: See application note SNOA549.

6.3 Recommended Operating Conditions

	MIN	TYP	MAX	UNIT
Supply Voltage (2.5V mode)	2.375	2.5	2.625	V
Supply Voltage (3.3V mode)	3.0	3.3	3.6	V
Ambient Temperature	-40	25	+85	°C
SMBus (SDA, SCL)			3.6	V
Supply Noise up to 50 MHz⁽¹⁾			100	mVp-p

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DS125BR401A	UNIT
		WQFN
		54 TERMINALS
R_θJA	Junction-to-ambient thermal resistance	26.6	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	10.8
R_θJB	Junction-to-board thermal resistance	4.4
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	4.3
R_θJCbot	Junction-to-case (bottom) thermal resistance	1.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER
I_DD	Current Consumption	DEM0 = Float, ,DEM1 = Float EQ = 0, VOD = 0.8VP-P, RXDET = 1, PWDN = 0		200	280	mA
I_DD	Power Down Current Consumption	PWDN = 1		14	27	mA
V_DD	Integrated LDO Regulator	V_IN = 3.0 - 3.6 V	2.375	2.5	2.625	V
LVCMOS / LVTTL DC SPECIFICATIONS
V_ih25	High Level Input Voltage	2.5 V Supply Mode	1.7		V_DD	V
V_ih33	High Level Input Voltage	3.3 V Supply Mode	1.7		V_IN	V
V_il	Low Level Input Voltage		0		0.7	V
V_oh	High Level Output Voltage (ALL_DONE Terminal)	I_oh = −4mA	2.0			V
V_ol	Low Level Output Voltage (ALL_DONE Terminal)	I_ol = 4mA			0.4	V
I_ih	Input High Current (PWDN Terminal)	V_IN = 3.6 V, LVCMOS = 3.6 V	-15		+15	uA
I_il	Input Low Current (PWDN Terminal)	V_IN = 3.6 V, LVCMOS = 0 V	-15		+15	uA
4-LEVEL INPUT DC SPECIFICATIONS
I_ih	Input High Current with internal resistors (4–level input Terminal)	V_IN = 3.6 V, LVCMOS = 3.6 V	+20		+150	uA
I_il	Input Low Current with internal resistors (4–level input Terminal)	V_IN = 3.6 V, LVCMOS = 0 V	-160		-40	uA
V_th	Threshold 0 / R	V_DD = 2.5V (2.5V supply mode) Internal LDO Disabled See Table 1 for details		0.45		V
	Threshold R / Float			1.2
	Threshold Float / 1			2
	Threshold 0 / R	V_IN = 3.3V (3.3V supply mode) Internal LDO Enabled See Table 1 for details.		0.6		V
	Threshold R / Float			1.6
	Threshold Float / 1			2.6
CML RECEIVER INPUTS (IN_n+, IN_n-)
RL_RX-diff	RX Differential return loss	SDD11 10 MHz		-19		dB
		SDD11 2 GHz		-14
		SDD11 6-11.1 GHz		-8
RL_RX-cm	RX Common mode return loss	0.05 - 5 GHz		-10		dB
Z_RX-dc	RX DC common mode impedance	Tested at VDD = 2.5 V	40	50	60	Ω
Z_RX-diff-dc	RX DC differential mode impedance	Tested at VDD = 2.5 V	80	100	120	Ω
V_{RX-signal-det-diff-pp}	Signal detect assert level for active data signal	SD_TH = F (float), 0101 pattern at 12 Gbps		50		mVp-p
V_{RX-idle-det-diff-pp}	Signal detect de-assert level for electrical idle	SD_TH = F (float), 0101 pattern at 12 Gbps		37		mVp-p
HIGH SPEED OUTPUTS
T_TX-RISE-FALL	Transmitter rise/fall time ⁽³⁾	20% to 80% of differential output voltage		40		ps
T_RF-MISMATCH	Transmitter rise/fall mismatch	20% to 80% of differential output voltage		0.01		UI
RL_TX-DIFF	TX Differential return loss	SDD22 10 MHz - 2 GHz		-15		dB
		SDD22 5.5 GHz		-12		dB
		SDD22 11.1 GHz		-10		dB
RL_TX-CM	TX Common mode return loss	0.05 - 5 GHz		-10		dB
Z_TX-DIFF-DC	DC differential TX impedance			100		Ω
I_TX-SHORT	Transmitter short circuit current limit	Total current, output shorted to VDD or GND		20		mA
V_{TX-CM-DC-ACTIVE-IDLE-DELTA}	Absolute delta of DC common mode voltage during L0 and electrical idle				100	mV
V_{TX-CM-DC-LINE-DELTA}	Absolute delta of DC common mode voltage between TX+ and TX-				25	mV
HIGH SPEED OUTPUTS (A-CHANNELS)
V_TXA-diff1-pp	Output Voltage Differential Swing	Differential measurement with OUTA_n+ and OUTA_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 600 mVp-p VOD = 001'b (800mV)	375	465	600	mVp-p
V_TXA-diff2-pp	Output Voltage Differential Swing	Differential measurement with OUTA_n+ and OUTA_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 1000 mVp-p VOD = 001'b (800mV)	550	675	825	mVp-p
V_TXA-diff3-pp	Output Voltage Differential Swing	Differential measurement with OUTA_n+ and OUTA_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 600 mVp-p DEMA[1:0] = 10, VOD = 1300mV	475	600	750	Vp-p
V_TXA-diff4-pp	Output Voltage Differential Swing	Differential measurement with OUTA_n+ and OUTA_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 1000 mVp-p VOD = 110'b (1300mV)	775	915	1125	Vp-p
T_{TXA-IDLE-DATA}	Time to transition to valid differential signal after idle	VID = 1.0 Vp-p, 3 Gbps		0.04		ns
T_{TXA-DATA-IDLE}	Time to transition to idle after differential signal	VID = 1.0 Vp-p, 3 Gbps		0.70		ns
T_PDEQA	Differential propagation delay - Channel A	EQ = Level 1 to Level 4		80		ps
HIGH SPEED OUTPUTS (B-CHANNELS)
V_TXB-diff1-pp	Output Voltage Differential Swing	Differential measurement with OUTB_n+ and OUTB_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 1.0 Vp-p, MODE_B = 1 DEMB1 = 0, DEMB0 = 1⁽⁴⁾	0.8	1.0	1.2	Vp-p
V_TXB-diff2-pp	Output Voltage Differential Swing	Differential measurement with OUTB_n+ and OUTB_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 1.0 Vp-p, MODE_B = 0 DEMB1 = 0, DEMB0 = R	670	820	930	mVp-p
V_TXB-diff3-pp	Output Voltage Differential Swing	Differential measurement with OUTB_n+ and OUTB_n-, AC-Coupled and terminated by 50Ω to GND, Inputs AC-Coupled, VID = 1.0 Vp-p, MODE_B = 0 DEMB1 = R, DEMB0 = FLOAT	950	1140	1250	mVp-p
V_{TXB-de-ratio_3.5}	TX de-emphasis ratio	VOD = 1.0 Vp-p, DEM0 = 0, DEM1 = R, MODE_B = 0 OUTB_n only Gen 1 & 2 mode		−3.5		dB
V_{TXB-de-ratio_6}	TX de-emphasis ratio	VOD = 1.0 Vp-p, DEM0 = R, DEM1 = R, MODE_B = 0 OUTB_n only in Gen 1 & 2 mode		−6		dB
T_{TXB-IDLE-DATA}	Time to transition to valid differential signal after idle	VID = 1.0 Vp-p, 3 Gbps		3.5		ns
T_{TXB-DATA-IDLE}	Time to transition to idle after differential signal	VID = 1.0 Vp-p, 3 Gbps		5.0		ns
T_PDEQB	Differential propagation delay - Channel B	EQ = 00⁽²⁾		135		ps
EQUALIZATION (A-CHANNELS)
DJE1A	Residual deterministic jitter at 6 Gbps	5” Differential Stripline, 5mil trace width, FR4, VID = 0.8 Vp-p, PRBS15, EQ = 01'h, VOD = 1.3V, DEM = 0 dB		0.06		UI
DJE3A	Residual deterministic jitter at 12 Gbps	5” Differential Stripline, 5mil trace width, FR4, VID = 0.8 Vp-p, PRBS15, EQ = 01'h, VOD = 1.3V, DEM = 0 dB		0.12		UI
EQUALIZATION (B-CHANNELS)
DJE1B	Residual deterministic jitter at 12 Gbps	30” Differential Stripline, 5mil trace width, FR4, VID = 0.6 Vp-p, PRBS15, EQ = 07'h, DEM = 0 dB		0.18		UI
DJE2B	Residual deterministic jitter at 12 Gbps	5 meters 30 awg cable, VID = 0.6 Vp-p, PRBS15, EQ = 07'h, DEM = 0 dB		0.25		UI
DE-EMPHASIS (B-CHANNELS, GEN 1&2 MODE ONLY)
DJD1	Residual deterministic jitter at 12 Gbps	Input Channel: 20" Differential Stripline, 5mil trace width, FR4, Output Channel: 10” Differential Stripline, 5mil trace width, FR4, VID = 0.6 Vp-p, PRBS15, EQ = 03'h, VOD = 1.0 Vp-p, DEMB = −3.5 dB		0.1		UI

(1) Allowed supply noise (mVp-p sine wave) under typical conditions.

(2) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation delays.

(3) Rise / Fall time measurements will on A-Channels will vary based on EQ setting, Input Amplitude, and input edge rate.

(4) In SAS-3 and PCIe GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output VOD level set by DEMA/B[1:0] in this mode BOUTn is dependent on the VID level and the frequency content. The DS125BR401A repeater is designed to be transparent in this mode, so the TX-FIR (de-emphasis) is passed to the RX to support the handshake negotiation link training.

6.6 Electrical Characteristics — Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
V_IL	Data, Clock Input Low Voltage				0.8	V
V_IH	Data, Clock Input High Voltage		2.1		3.6	V
V_OL	Output Low Voltage	SDA or SCL, I_OL = 1.25 mA	0		0.36	V
V_DD	Nominal Bus Voltage		2.375		3.6	V
I_IH-Terminal	Input Leakage Per Device Terminal		+20		+150	µA
I_IL-Terminal	Input Leakage Per Device Terminal		-160		-40	µA
C_I	Capacitance for SDA and SCL	See⁽¹⁾⁽²⁾		< 5		pF
R_TERM	External Termination Resistance pull to V_DD = 2.5V ± 5% OR 3.3V ± 10%	Pullup V_DD = 3.3V⁽¹⁾⁽²⁾⁽³⁾		2000		Ω
R_TERM		Pullup V_DD = 2.5V⁽¹⁾⁽²⁾⁽³⁾		1000		Ω

(1) Recommended value.

(2) Recommended maximum capacitance load per bus segment is 400pF.

(3) Maximum termination voltage should be identical to the device supply voltage.

6.7 Timing Requirements Serial Bus Interface

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB	Bus Operating Frequency	ENSMB = VDD (Slave Mode)			400	kHz
FSMB	Bus Operating Frequency	ENSMB = FLOAT (Master Mode)	280	400	520	kHz
t_FALL	SDA Fall Time	Read operation RPU = 4.7K, Cb < 50pF		60		ns
t_RISE	SDA Rise Time	Read operation RPU = 4.7K, Cb < 50pF		140		ns
t_F	Clock/Data Fall Time	See⁽¹⁾			300	ns
t_R	Clock/Data Rise Time	See⁽¹⁾			1000	ns

(1) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details.