米6体育平台手机版

ZHCSD85F August 2012 – November 2018 DS125BR800

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

NJY|54
- MPQS027A

散热焊盘机械数据 (封装 | 引脚)

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7.7 Timing Requirements

			MIN	TYP	MAX	UNIT
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB	Bus Operating Frequency⁽¹⁾	ENSMB = VDD (Slave Mode)			400	kHz
FSMB	Bus Operating Frequency⁽¹⁾	ENSMB = FLOAT (Master Mode)	280	400	520	kHz
TBUF	Bus Free Time Between Stop and Start Condition		1.3			µs
THD:STA	Hold time after (Repeated) Start Condition. After this period, the first clock is generated.	At I_PULLUP, Max	0.6			µs
TSU:STA	Repeated Start Condition Setup Time		0.6			µs
TSU:STO	Stop Condition Setup Time		0.6			µs
THD:DAT	Data Hold Time		0			ns
TSU:DAT	Data Setup Time		100			ns
T_LOW	Clock Low Period		1.3			µs
T_HIGH	Clock High Period	⁽²⁾	0.6		50	µs
t_F	Clock/Data Fall Time	⁽²⁾			300	ns
t_R	Clock/Data Rise Time	⁽²⁾			300	ns
t_POR	Time in which a device must be operational after power-on reset	⁽²⁾⁽³⁾			500	ms

(1) In Master Mode, a serial EEPROM with a minimum rating of 520 KHz is required.

(2) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details.

(3) Specified by Design. Parameter not tested in production.

Figure 1. CML Output and Rise and FALL Transition Time

Figure 2. Propagation Delay Timing Diagram

Figure 3. Transmit IDLE-DATA and DATA-IDLE Response Time

Figure 4. SMBus Timing Parameters