ZHCSD85F August   2012  – November 2018 DS125BR800

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics: Serial Management Bus Interface
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
      2. 8.3.2 PCIe Signal Integrity
        1. 8.3.2.1 RX-Detect in SAS/SATA (up to 6 Gbps) Applications
          1. 8.3.2.1.1 Signal Detect Control for Datarates above 8 Gbps
        2. 8.3.2.2 MODE Operation with SMBus Registers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Mode
    5. 8.5 Programming
      1. 8.5.1 SMBus Master Mode
      2. 8.5.2 Transfer of Data Via the SMBus
      3. 8.5.3 System Management Bus (SMBus) and Configuration Registers
      4. 8.5.4 SMBus Transactions
      5. 8.5.5 Writing a Register
      6. 8.5.6 Reading a Register
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.2 PCIe Signal Integrity

When using the DS125BR800 in PCIe Gen-3 systems, there are specific signal integrity settings to ensure signal integrity margin. The settings were achieved with completing extensive testing. Contact your field representative for more information regarding the testing completed to achieve these settings.

For tuning the in the downstream direction (from CPU to EP).

  • EQ: use the guidelines outlined in Table 2.
  • De-Emphasis: use the guidelines outlined in Table 3.
  • VOD: use the guidelines outlined in Table 3.

For tuning in the upstream direction (from EP to CPU).

  • EQ: use the guidelines outlined in Table 2.
  • De-Emphasis:
    • For trace lengths < 15" set to -3.5 dB
    • For trace lengths > 15" set to -6 dB
  • VOD: set to 900 mV

Table 2. Equalizer Settings

Level EQA1
EQB1		 EQA0
EQB		 EQ – 8 bits [7:0] dB at
1.5 GHz		 dB at
2.5 GHz		 dB at
4 GHz		 dB at
6 GHz		 Suggested Use(1)
1 0 0 0000 0000 = 0x00 2.5 3.5 3.8 3.1 FR4 < 5 inch trace
2 0 R 0000 0001 = 0x01 3.8 5.4 6.7 6.7 FR4 5-10 inch trace
3 0 Float 0000 0010 = 0x02 5.0 7.0 8.4 8.4 FR4 10 inch trace
4 0 1 0000 0011 = 0x03 5.9 8.0 9.3 9.1 FR4 15-20 inch trace
5 R 0 0000 0111 = 0x07 7.4 10.3 12.8 13.7 FR4 20-30 inch trace
6 R R 0001 0101 = 0x15 6.9 10.2 13.9 16.2 FR4 25-30 inch trace
7 R Float 0000 1011 = 0x0B 9.0 12.4 15.3 15.9 FR4 25-30 inch trace
8 R 1 0000 1111 = 0x0F 10.2 13.8 16.7 17.0 8m, 30awg cable
9 Float 0 0101 0101 = 0x55 8.5 12.6 17.5 20.7 > 8m cable
10 Float R 0001 1111 = 0x1F 11.7 16.2 20.3 21.8
11 Float Float 0010 1111 = 0x2F 13.2 18.3 22.8 23.6
12 Float 1 0011 1111 = 0x3F 14.4 19.8 24.2 24.7
13 1 0 1010 1010 = 0xAA 14.4 20.5 26.4 28.0
14 1 R 0111 1111 = 0x7F 16.0 22.2 27.8 29.2
15 1 Float 1011 1111 = 0xBF 17.6 24.4 30.2 30.9
16 1 1 1111 1111 = 0xFF 18.7 25.8 31.6 31.9
(1) Cable and FR4 lengths are for reference only. FR4 lengths based on a 100 Ω differential stripline with 5-mil traces and 8-mil trace separation. Optimal EQ setting should be determined via simulation and prototype verification.

Table 3. Output Voltage and De-Emphasis Settings

Level DEMA1
DEMB1		 DEMA0
DEMB0		 VOD Vp-p DEM dB(1) Inner Amplitude
Vp-p		 Suggested Use(2)
1 0 0 0.8 0 0.8 FR4 < 5 inch 4–mil trace
2 0 R 0.9 0 0.9 FR4 < 5 inch 4–mil trace
3 0 Float 0.9 - 3.5 0.6 FR4 10 inch 4–mil trace
4 0 1 1.0 0 1.0 FR4 < 5 inch 4–mil trace
5 R 0 1.0 - 3.5 0.7 FR4 10 inch 4–mil trace
6 R R 1.0 - 6 0.5 FR4 15 inch 4–mil trace
7 R Float 1.1 0 1.1 FR4 < 5 inch 4–mil trace
8 R 1 1.1 - 3.5 0.7 FR4 10 inch 4–mil trace
9 Float 0 1.1 - 6 0.6 FR4 15 inch 4–mil trace
10 Float R 1.2 0 1.2 FR4 < 5 inch 4–mil trace
11 Float Float 1.2 - 3.5 0.8 FR4 10 inch 4–mil trace
12 Float 1 1.2 - 6 0.6 FR4 15 inch 4–mil trace
13 1 0 1.3 0 1.3 FR4 < 5 inch 4–mil trace
14 1 R 1.3 - 3.5 0.9 FR4 10 inch 4–mil trace
15 1 Float 1.3 - 6 0.7 FR4 15 inch 4–mil trace
16 1 1 1.3 - 9 0.5 FR4 20 inch 4–mil trace
(1) The VOD output amplitude and DEM de-emphasis levels are set with the DEMA/B[1:0] pins.
The de-emphasis levels are available in PCIe Gen-3 modes when MODE = 1 (tied to VIN)
(2) FR4 lengths are for reference only. FR4 lengths based on a 100 Ω differential stripline with 5-mil traces and 8-mil trace separation. Optimal DEM settings should be determined via simulation and prototype verification.

Table 4. RX-Detect Settings

PWDN
(PIN 52)		 RXDET
(PIN 22)		 SMBus REG
bit [3:2]		 Input Termination Recommeded Use Comments
0 0 00 Hi-Z X Manual RX-Detect, input is high impedance mode
0 Tie 20 kΩ
to GND		 01 Pre Detect: Hi-Z
Post Detect: 50 Ω		 PCIe Only Auto RX-Detect, outputs test every 12 msec for 600 msec then stops; termination is Hi-Z until detection; once detected input termination is 50 Ω.

Reset function by pulsing PWDN high for 5 µsec then low again
0 Float
(Default)		 10 Pre Detect: Hi-Z
Post Detect: 50 Ω		 PCIe Only Auto RX-Detect, outputs test every 12 msec until detection occurs; termination is Hi-Z until RX detection; once detected input termination is 50 Ω.
0 1 11 50 Ω All Others Manual RX-Detect, input is 50 Ω.
1 X High Impedance X Power down mode, input is Hi-Z, output drivers are disabled.

Used to reset RX-Detect State Machine when held high for 5 µsec.
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