ZHCSRO2 February   2023 DS160PR1601

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Control and Configuration Interface
      1. 7.3.1 Pin Configurations for Lanes
        1. 7.3.1.1 Five-Level Control Inputs
      2. 7.3.2 SMBUS/I2C Register Control Interface
      3. 7.3.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
    4. 7.4 Feature Description
      1. 7.4.1 Linear Equalization
      2. 7.4.2 Flat-Gain
      3. 7.4.3 Analog EyeScan
      4. 7.4.4 Receiver Detect State Machine
      5. 7.4.5 Integrated Capacitors
    5. 7.5 Device Functional Modes
      1. 7.5.1 Active PCIe Mode
      2. 7.5.2 Active Buffer Mode
      3. 7.5.3 Standby Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

7.4.1 Linear Equalization

The DS160PR1601 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. The device has 20 available equalization boost settings that can be set though SMBus/I2C registers. #GUID-2E005092-474B-4D50-ABBC-906BDD001AA0/T5706319-21 shows the device EQ settings.

Refer to the DS160PR1601 Programming Guide for detail register sets and control configuration procedures.
Table 7-4 Equalization Control Settings
EQ INDEX TYPICAL EQ BOOST (dB) at 8 GHz
0 2.0
1 3.5
2 5.0
3 7.0
4 8.0
5 9.0
6 9.8
7 10.2
8 10.8
9 11.2
10 11.8
11 12.2
12 12.8
13 13.2
14 13.8
15 14.2
16 14.8
17 15.2
18 15.6
19 16.0
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