ZHCSRO2 February 2023 DS160PR1601
PRODUCTION DATA
If MODE = L2 (SMBus / I2C secondary control mode), the DS160PR1601 is configured through a standard I2C or SMBus interface that may operate up to 400 kHz. The device also can be configured through loading settings from EEPROM. The SMBus / I2C primary / secondary address of the DS160PR1601 is determined by the pin strap settings on the xADDRx pins. Note addresses to access differental channels are different. To illustrate A_ADDR1_15_8 and A_ADDR0_15_8 sets the primary / secondary address for bank of lanes 15-12 and 11-8 of Side A, while A_ADDR1_7_0 and A_ADDR0_7_0 sets for bank of lanes 7-4 and 3-0 of Side A. B side address is also set similarly. #GUID-8C193560-770C-4C55-8666-8C22A52C1EE4/TABLE_QHX_CYZ_CPB show SMBus / I2C primary / secondary addresses.
| x_ADDR1_x | x_ADDR0_x |
7-bit address Upper (for Side A) / Lower (for Side B) 4 Lanes of each Bank |
7-bit address Lower (for Side A) / Upper (for Side B) 4 Lanes of each Bank |
|---|---|---|---|
| L0 | L0 | 0x19 | 0x18 |
| L0 | L1 | 0x1B | 0x1A |
| L0 | L2 | 0x1D | 0x1C |
| L0 | L3 | 0x1F | 0x1E |
| L0 | L4 | Reserved | Reserved |
| L1 | L0 | 0x21 | 0x20 |
| L1 | L1 | 0x23 | 0x22 |
| L1 | L2 | 0x25 | 0x24 |
| L1 | L3 | 0x27 | 0x26 |
| L1 | L4 | Reserved | Reserved |
| L2 | L0 | 0x29 | 0x28 |
| L2 | L1 | 0x2B | 0x2A |
| L2 | L2 | 0x2D | 0x2C |
| L2 | L3 | 0x2F | 0x2E |
| L2 | L4 | Reserved | Reserved |
| L3 | L0 | 0x31 | 0x30 |
| L3 | L1 | 0x33 | 0x32 |
| L3 | L2 | 0x35 | 0x34 |
| L3 | L3 | 0x37 | 0x36 |
| L3 | L4 | Reserved | Reserved |
In SMBus/I2C modes the SCL, SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 50 pF.
Refer to the DS160PR1601 Programming Guide for detail register sets and control configuration procedures.