ZHCSK36 August 2019 DS160PR410
ADVANCE INFORMATION for pre-production products; subject to change without notice.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Power | ||||||
IACTIVE | Device current consumption when all four channels are active | All four channels enabled with VOD = L2 | 150 | 200 | mA | |
IACTIVE-HALF | Device current consumption when two channels are active | Two channels enabled with VOD = L2, PWDN1 or PWDN2=L | 85 | 110 | mA | |
ISTBY | Device current consumption in standby power mode | All four channels disabled (PWDN1,2 = H) | 26 | 33 | mA | |
VREG | Internal regulator output | 2.5 | V | |||
Control IO | ||||||
VIH | High level input voltage | SDA, SCL, PWDN1, PWDN2, READ_EN_N pins | 2.1 | V | ||
VIL | Low level input voltage | SDA, SCL, PWDN1, PWDN2, READ_EN_N pins | 1.08 | V | ||
VOH | High level output voltage | Rpull-up = 100K (SDA, SCL, ALL_DONE_N pins) | 2 | V | ||
VOL | Low level output voltage | IOL = –4 mA (SDA, SCL, ALL_DONE_N pins) | 0.4 | V | ||
IIH | Input high leakage current | VInput = VDD, (SCL, SDA, PWDN1, PWDN2, READ_EN_N pins) | 10 | µA | ||
IIL | Input low leakage current | VInput = 0 V, (SCL, SDA, PWDN1, PWDN2, READ_EN_N pins) | -10 | µA | ||
CIN-CTRL | Input capacitance | 1.5 | pF | |||
4 Level IOs (EQ0_ADDR0, EQ1_ADDR1, EN_SMB, RX_DET, VOD, GAIN pins) | ||||||
IIH_4L | Input high leakage current, 4 level IOs | VIN=2.5V | 10 | µA | ||
IIL_4L | Input low leakage current, , 4 level IOs | VIN=GND | -150 | µA | ||
Receiver | ||||||
ZRX-DC | Rx DC Single-Ended Impedance | 50 | Ω | |||
ZRX-DIFF-DC | Rx DC Differential Impedance | 100 | Ω | |||
Transmitter | ||||||
ZTX-DIFF-DC | DC Differential Tx Impedance | Impedance of Tx during active signaling, VID,diff=1Vpp | 100 | Ω | ||
ITX-SHORT | Tx Short Circuit Current | Total current the Tx can supply when shorted to GND | 90 | mA |