ZHCSME1C August   2018  – June 2021 DS250DF230

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
        1. 8.3.7.1 CDR Bypass (Raw) Mode
        2. 8.3.7.2 CDR Fast Lock Mode
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver With FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
        3. 8.3.9.3 Slow Slew Rate
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye-Opening Monitor
      11. 8.3.11 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Backplane and Mid-Plane Applications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
  13. 13Electrostatic Discharge Caution
  14. 14术语表
  15. 15Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization

The output differential voltage (VOD), pre-cursor, and post-cursor equalization of the driver is controlled by manipulating the FIR tap settings. The main cursor tap is the primary knob for amplitude adjustment. The pre- and post-cursor FIR tap settings can then be adjusted to provide equalization. To maintain a constant peak-to-peak VOD, the user must adjust the main cursor tap value relative to the pre- and post-cursor tap changes so as to maintain a constant absolute sum of the FIR tap values. Table 8-2 shows various settings for VOD settings ranging from 350 mVpp to 1195 mVpp (typical). Note that the output peak-to-peak amplitude is a function of the sum of the absolute values of the taps, whereas the low-frequency amplitude is purely a function of the main-cursor value.

Table 8-2 Typical VOD and FIR Values
FIR SETTINGSPeak-to Peak VOD(V)RPRE(dB)RPST(dB)
PRE-CURSOR:
REG_0x3E[6:0]		MAIN-CURSOR:
REG_0x3D[6:0]		POST-CURSOR:
REG_0x3F[6:0]
0+300.350NANA
0+400.392NANA
0+500.436NANA
0+600.482NANA
0+700.524NANA
0+800.562NANA
0+900.602NANA
0+1000.638NANA
0+1100.678NANA
0+1200.710NANA
0+1300.748NANA
0+1400.782NANA
0+1500.816NANA
0+1600.846NANA
0+1700.880NANA
0+1800.910NANA
0+1900.944NANA
0+2000.968NANA
0+2100.998NANA
0+2201.028NANA
0+2301.056NANA
0+2401.076NANA
0+2501.096NANA
0+2601.120NANA
0+2701.140NANA
0+2801.155NANA
0+2901.175NANA
0+3001.185NANA
0+3101.195NANA
0+16–10.880NA2.0
0+15–20.880NA2.7
0+14–30.880NA3.4
0+13–40.880NA4.3
0+12–50.880NA5.4
0+11–60.880NA6.7
0+10–70.880NA8.4
0+9–80.880NA11
-1+1600.8800.7NA
-2+1500.8801.5NA
-3+1400.8802.5NA
-4+1300.8803.5NA
0+30–11.195NA0.6
0+29–21.195NA0.8
0+28–31.195NA1.1
0+27–41.195NA1.4
0+26–51.195NA1.8
0+25–61.195NA2.3
0+24–71.195NA2.8
0+23–81.195NA3.4
0+22–91.195NA4.1
0+21–101.195NA4.9
0+20–111.195NA5.9
0+19–121.195NA6.9
-1+3001.1950.4NA
-2+2901.1950.6NA
-3+2801.1950.9NA
-4+2701.1951.3NA
-5+2601.1951.7NA
-6+2501.1952.1NA
-7+2401.1952.7NA

The recommended pre-cursor and post-cursor settings for a given channel will depend on the channel characteristics (mainly insertion loss) as well as the equalization capabilities of the downstream receiver. The DS250DF230 receiver, with its highly-capable CTLE and DFE, does not require a significant amount of pre- or post-cursor. The guidelines in Figure 8-5 through Figure 8-7 give general recommendations for pre- and post-cursor for different channel loss conditions. The insertion loss (IL) in these plots refers to the total loss between the link partner transmitter and the DS250DF230 receiver.

GUID-38DFEBB6-766B-4B94-9ED9-3CBEBEA972A9-low.gifFigure 8-5 Guideline for Link Partner FIR Settings When IL ≤ 15 dB
GUID-B12DFCA3-5999-4C53-94B2-C5FCBB7D1346-low.gifFigure 8-6 Guideline for Link Partner FIR Settings When IL ≤ 25 dB
GUID-5506C8B0-307B-4F13-A533-0F9BD1ADCBE6-low.gifFigure 8-7 Guideline for Link Partner FIR Settings When IL ≤ 35 dB
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |