ZHCSME1C August   2018  – June 2021 DS250DF230

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
        1. 8.3.7.1 CDR Bypass (Raw) Mode
        2. 8.3.7.2 CDR Fast Lock Mode
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver With FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
        3. 8.3.9.3 Slow Slew Rate
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye-Opening Monitor
      11. 8.3.11 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Backplane and Mid-Plane Applications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
  13. 13Electrostatic Discharge Caution
  14. 14术语表
  15. 15Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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9.2.2.1 Design Requirements

For this design example, the following guidelines outlined in Table 9-2 and Table 9-3 apply.

Table 9-2 Half-Active Cable Application Design Guidelines
DESIGN PARAMETERREQUIREMENT
Device placementPlace the DS250DF230s on the receive side of the paddle card such that it is receiving data from the cable, and transmitting towards the host.
AC-coupling capacitors100-nF, AC-coupling capacitors are required for the RX inputs and the TX outputs.
Cable insertion lossThe raw cable insertion loss including the insertion loss of the paddle card must be ≤ 27 dB at 25.78125-Gbps Nyquist frequency (12.9 GHz). This is to ensure that the total loss at the input to the DS250DF230 is ≤ 35 dB at 12.9 GHz. Assuming a worst-case host-side PCB loss of 7 dB, plus a connector loss of 1 dB, the remaining loss allocated for the raw cable and paddle cards is 27 dB.
Table 9-3 Full-Active Cable Application Design Guidelines
DESIGN PARAMETERREQUIREMENT
Device placementA full-active QSFP cable will uses 4 pieces of DS250DF230 per paddle card. Typically, two devices will be placed on each side of the paddle card.
AC-coupling capacitorsTransmit-side Retimer: 100-nF, AC coupling capacitors are required for the RX inputs and are not required for the TX outputs. This link segment will be AC coupled on the paddle card at the opposite end of the cable.
Receive-side Retimer: 100-nF, AC-coupling capacitors are required for the RX inputs and the TX outputs.
Cable insertion lossThe raw cable insertion loss including the insertion loss of the paddle card must be ≤ 35 dB at 25.78125-Gbps Nyquist frequency (12.9 GHz).
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