The calibration clock is not part of the CDR’s PLL and thus is not used for clock and data recovery. The calibration clock is connected only to the PPM counter for each CDR. The PPM counter constrains the allowable lock ranges of the CDR according to the programmed values in the rate table or the manually entered data rates. The host must provide an input calibration clock signal of 30.72-MHz or 25-MHz frequency. This clock is not used for clock and data recovery, thus there are no stringent jitter requirements placed on this calibration clock.