ZHCSME1C August   2018  – June 2021 DS250DF230

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
        1. 8.3.7.1 CDR Bypass (Raw) Mode
        2. 8.3.7.2 CDR Fast Lock Mode
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver With FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
        3. 8.3.9.3 Slow Slew Rate
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye-Opening Monitor
      11. 8.3.11 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Backplane and Mid-Plane Applications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
  13. 13Electrostatic Discharge Caution
  14. 14术语表
  15. 15Mechanical, Packaging, and Orderable Information

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订购信息

Eye-Opening Monitor

The DS250DF230’s Eye-Opening Monitor (EOM) measures the internal data eye at the input of the decision slicer and can be used for 2 functions:

  1. Horizontal Eye Opening (HEO) and Vertical Eye Opening (VEO) measurement
  2. Full Eye Diagram Capture

The HEO measurement is made at the 0 V crossing and is read in channel register 0x27. The VEO measurement is made at the 0.5 UI mark and is read in channel register 0x28. The HEO and VEO registers can be read from channel registers 0x27 and 0x28 at any time while the CDR is locked. The following equations are used to convert the contents of channel registers 0x27 and 0x28 into their appropriate units:

  • HEO [UI] = Reg_0x27 ÷ 32
  • VEO [mV] = Reg_0x28 × 3.125

A full eye diagram capture can be performed when the CDR is locked. The eye diagram is constructed within a 64 × 64 array, where each cell in the matrix consists of an 16-bit word representing the total number of hits recorded at that particular phase and voltage offset. Users can manually adjust the vertical scaling of the EOM or allow the state machine to control the scaling which is the default option. The horizontal scaling controlled by the state machine is always directly proportional to the data rate.

When a full eye diagram plot is captured, the retimer will shift out four 16-bit words of residual data that must be discarded followed by 4096 16-bit words that make up the 64 × 64 eye plot. The first actual word of the eye plot from the retimer is for (X, Y) position (0,0), which is the earliest position in time and the most negative position in voltage. Each time the eye plot data is read out, the voltage position is incremented. Once the voltage position has incremented to position 63 (the most positive voltage), the next read will cause the voltage position to reset to 0 (the most negative voltage) and the phase position to increment. This process will continue until the entire 64 × 64 matrix is read out. Figure 8-8 shows the EOM read out sequence overlaid on top of a simple eye opening plot. In this plot any hits are shown in green. This type of plot is helpful for quickly visualizing the HEO and VEO. Users can apply different algorithms to the output data to plot density or color gradients to the output data.

GUID-FBD67F42-18CA-4F3F-98CB-D2B9A3BFA230-low.gif Figure 8-8 EOM Full Eye Capture Readout

To manually control the EOM vertical range, remove scaling control from the state machine then select the desired range:

Channel Reg 0x2C[6] → 0 (see Table 8-3).

Table 8-3 Eye-Opening Monitor Vertical Range Settings
CH REG 0x11[7:6] VALUEEOM VERTICAL RANGE [mV]
2’b00±100
2'b01±200
2'b10±300
2'b11±400

The EOM operates as an under-sampled circuit. This allows the EOM to be useful in identifying over equalization, ringing and other gross signal conditioning issues. However, the EOM cannot be correlated to a bit error rate.

The EOM can be accessed in two ways to read out the entire eye plot:

  • Multi-byte reads can be used such that data is repeatedly latched out from channel register 0x25.
  • With single byte reads, the MSB are located in register 0x25 and the LSB are located in register 0x26. In this mode, the device must be addressed each time a new byte is read.

To perform a full eye capture with the EOM, follow the steps listed in Table 8-4 within the desired channel register set:

Table 8-4 Eye-Opening Monitor Full Eye Capture Instructions
STEPREGISTER [bits]OperationVALUEDESCRIPTION
10x67[5]Write0Disable lock EOM lock monitoring
20x2C[6]Write0Set the desired EOM vertical range
0x11[7:6]Write2'b--
30x11[5]Write0Power on the EOM
40x24[7]Write1Enable fast EOM
50x24[0]
0x25
0x26
Read1Begin read out of the 64 × 64 array, discard first 4 words
Ch reg 0x24[0] is self-clearing.
0x25 is the MSB of the 16-bit word
0x26 is the LSB of the 16-bit word
60x25ReadContinue reading information until the 64 × 64 array is complete.
0x26
70x67[5]Write1Return the EOM to its original state. Undo steps 1-4
0x2C[6]Write1
0x11[5]Write1
0x24[7]Write0