The CDR consists of a Phase-Locked Loop (PLL), PPM counter, and Input and Output Data Multiplexers (mux) that allow for retimed data, non-retimed data, a PRBS generator, and output muted modes.

By default, the equalized data is fed into the CDR for clock and data recovery. The recovered data is then output to the FIR filter and differential driver together with the recovered clock that was cleaned of any high-frequency jitter outside the bandwidth of the CDR clock recovery loop. The bandwidth of the CDR defaults to 4.7 MHz (typical) in full-rate (divide-by-1) mode and 4 MHz (typical) in sub-rate mode. The CDR bandwidth is adjustable. Refer to the DS250DF230 Programmer's Guide (SNLU182) for more information on adjusting the CDR bandwidth. Users can configure the CDR data to route the recovered clock and data to the PRBS checker. Users also have the option of configuring the output of the CDR to send raw non-retimed data, or data from the pattern generator.

The CDR requires these items for proper configuration:

• A 30.72-MHz or 25-MHz calibration clock to run the PPM counter (CAL_CLK_IN).
• Expected data rates must be programmed into the CDR either through the rate table or entered manually with the corrected divider settings. Refer to the DS250DF230 Programmer's Guide (SNLU182) for more information on configuring the CDR for different data rates.

The DS250DF230 offers a low-speed recovered clock for channel 0. This feature is useful for the cases when recovered clock from FPGA or ASIC has in-band spurs on the phase noise plot because of the digital switching noise. See the Table 8-6 for the recovered clock frequency versus input data rate.