ZHCSKE8D March 2016 – October 2019 DS250DF410
PRODUCTION DATA.
For this design example, the following guidelines outlined in Table 12 apply.
| DESIGN PARAMETER | REQUIREMENT |
|---|---|
| AC coupling capacitors | Egress (ASIC-to-module) direction: AC coupling capacitors in the range of 100 to 220 nF are required for the RX inputs and are NOT required for the TX outputs.
Ingress (module-to-ASIC) direction: AC coupling capacitors in the range of 100 to 220 nF are required for the TX outputs and are NOT required for the RX inputs. |
| Input channel insertion loss | ≤ 35 dB at 25.78125 Gbps Nyquist frequency (12.9 GHz) |
| Output channel insertion loss | Egress (ASIC-to-module) direction: Follow CAUI-4 / CEI-25G-VSR host channel requirements (approximately 7dB at 12.9 GHz).
Ingress (module-to-ASIC) direction: Depends on downstream ASIC / FPGA capabilities. The DS250DF410 has a low-jitter output driver with 3-tap FIR filter for equalizing a portion of the output channel. |
| Host ASIC TX launch amplitude | 800 mVppd to 1200 mVppd. |
| Host ASIC TX FIR filter | Depends on channel loss. Refer to Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization. |