11.1 Layout Guidelines

The following guidelines should be followed when designing the layout:

1. Decoupling capacitors should be placed as close to the VDD pins as possible. Placing them directly underneath the device is one option if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and impedance controlled.
3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, care should be taken to minimize the via stub, either by transitioning through most/all layers, or by back drilling.
4. GND relief can be used beneath the high-speed differential signal pads to improve signal integrity by counteracting the pad capacitance.
5. GND relief can be used beneath the AC coupling capacitor pads to improve signal integrity by counteracting the pad capacitance.
6. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to the GND planes on other layers. This has the added benefit of improving thermal conductivity from the device to the board
7. BGA landing pads for a 0.5-mm pitch flip-chip BGA are typically 0.3 mm in diameter (exposed). The actual size of the copper pad will depend on whether solder-mask-defined (SMD) or non-solder-mask-defined solder land pads are used. For more information, refer to TI’s Surface Mount Technology (SMT) and Packaging application notes on the TI website.
8. If vias are used for the high-speed signals, ground via should be implemented adjacent to the signal via to provide return path and isolation. For differential pair, the typical via configuration is ground-signal-signal-ground.
9. Note that some BGA balls in the DS250DF410 pinout have been de-populated to allow for GND and VDD vias to be placed with ≥1.0 mm via-to-via spacing.