11.2 Layout Example

The following example layout demonstrates how all signals can be escaped from the BGA array using microstrip routing on a generic multi-layer stackup. This example layout assumes the following:

• Trace width: 0.159 mm (6.25 mil)
• Trace edge-to-edge spacing: 0.197 mm (7.75 mil)
• VIA-to-VIA spacing: 0.7 mm (27.9 mil) minimum; Note: 1.0 mm VIA-to-VIA spacing is also achievable if PCB manufacturing rules stipulate
• No VIA-in-pad used
• Note: Some TI test pins (i.e. NC_TEST[5:0]) are routed in this example layout, but in most applications these pins can be left floating.

Note that many other escape routing options exist using different trace width and spacing combinations. The optimum trace width and spacing will depend on the PCB material, PCB routing density, and other factors.

Figure 25. Top Layer

Figure 27. Internal Low-Speed Signal Layers

Figure 29. Bottom Layer

Figure 26. Layer 1 GND

Figure 28. VDD Layer