ZHCSKG1C November 2015 – October 2019 DS280BR810
PRODUCTION DATA.
For backplane and mid-plane reach extension application, use the guidelines in the table below.
| DESIGN PARAMETER | REQUIREMENT |
|---|---|
| AC Coupling Capacitors | Not required. 220 nF AC coupling capacitors are included in the device package on both the RX and TX side. |
| Input Channel Insertion Loss | ≥ 10 dB at 14 GHz as a rough guideline. For best performance, the input channel insertion loss should be greater than or equal to the equalizer boost setting used in the DS280BR810. |
| Output Channel Insertion Loss | Depends on downstream ASIC and FPGA SerDes capabilities. Should be ≥ 5 dB at 14 GHz as a rough guideline. |
| Total (Input + Output) Channel Insertion Loss | Depends on downstream ASIC and FPGA SerDes capabilities. The DS280BR810 can extend the reach between two ASICs by 15 to 20 dB beyond the ASICs' normal capabilities. |
| Link Partner TX Launch Amplitude | 800 mVPP to 1200 mVPP differential |
| Link Partner TX FIR Filter | Depends on the channel loss. |