ZHCSKG2B September 2016 – October 2019 DS280BR820
PRODUCTION DATA.
The DS280BR820’s SMBus slave address is strapped at power up using the ADDR[1:0] pins. The pin state is read on power up, after the internal power-on reset completes. The ADDR[1:0] pins are four-level LVCMOS IOs, which provide for 16 unique SMBus addresses. Table 1 lists the DS280BR820 SMBus slave address options.
| 7-BIT SLAVE ADDRESS | 8-BIT WRITE ADDRESS | REQUIRED ADDRESS PIN STRAP VALUE | |
|---|---|---|---|
| ADDR1 | ADDR0 | ||
| 0x18 | 0x30 | 0 | 0 |
| 0x19 | 0x32 | 0 | R |
| 0x1A | 0x34 | 0 | F |
| 0x1B | 0x36 | 0 | 1 |
| 0x1C | 0x38 | R | 0 |
| 0x1D | 0x3A | R | R |
| 0x1E | 0x3C | R | F |
| 0x1F | 0x3E | R | 1 |
| 0x20 | 0x40 | F | 0 |
| 0x21 | 0x42 | F | R |
| 0x22 | 0x44 | F | F |
| 0x23 | 0x46 | F | 1 |
| 0x24 | 0x48 | 1 | 0 |
| 0x25 | 0x4A | 1 | R |
| 0x26 | 0x4C | 1 | F |
| 0x27 | 0x4E | 1 | 1 |