ZHCSKG3B September   2016  – February 2024 DS280DF810

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, Retimer Jitter Specifications
    7. 5.7  Timing Requirements, Retimer Specifications
    8. 5.8  Timing Requirements, Recommended Calibration Clock Specifications
    9. 5.9  Recommended SMBus Switching Characteristics (Target Mode)
    10. 5.10 Recommended SMBus Switching Characteristics (Controller Mode)
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Data Path Operation
        1. 6.3.1.1 AC-Coupled Receiver and Transmitter
        2. 6.3.1.2 Signal Detect
        3. 6.3.1.3 Continuous Time Linear Equalizer (CTLE)
        4. 6.3.1.4 Variable Gain Amplifier (VGA)
        5. 6.3.1.5 2x2 Cross-Point Switch
        6. 6.3.1.6 Decision Feedback Equalizer (DFE)
        7. 6.3.1.7 Clock and Data Recovery (CDR)
        8. 6.3.1.8 Calibration Clock
        9. 6.3.1.9 Differential Driver with FIR Filter
          1. 6.3.1.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
          2. 6.3.1.9.2 Output Driver Polarity Inversion
      2. 6.3.2 Debug Features
        1. 6.3.2.1 Pattern Generator
        2. 6.3.2.2 Pattern Checker
        3. 6.3.2.3 Eye Opening Monitor
        4. 6.3.2.4 Interrupt Signals
    4. 6.4 Device Functional Modes
      1. 6.4.1 Supported Data Rates
      2. 6.4.2 SMBus Controller Mode
      3. 6.4.3 42
      4. 6.4.4 Device SMBus Address
    5. 6.5 Programming
      1. 6.5.1 Bit Fields in the Register Set
      2. 6.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Backplane and Mid-Plane Reach Extension Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Front-Port Jitter Cleaning Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABW|135
  • ABV|135
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.6 Timing Requirements, Retimer Jitter Specifications

Over operating free-air temperature range (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
JTJOutput Total jitter (TJ)Measured at 28.4Gbps to a probability level of 1E-15 with PRBS9 data pattern an evaluation board traces de-embedded.0.24UIpp @ 1E-12
JRJOutput Random Jitter (RJ)Measured at 28.4Gbps to a probability level of 1E-15 with PRBS9 data pattern an evaluation board traces de-embedded8mUI RMS
JDCDOutput Duty Cycle Distortion (DCD)Measured at 28.4Gbps to a probability level of 1E-15 with PRBS9 data pattern an evaluation board traces de-embedded15mUIpp
JTJOutput Total jitter (TJ)Measured at 25.78125Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded.0.17UIpp @ 1E-12
JRJOutput Random Jitter (RJ)Measured at 25.78125Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded6mUI RMS
JDCDOutput Duty Cycle Distortion (DCD)Measured at 25.78125Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded4mUIpp
JPEAKJitter peakingMeasured at 10.3125Gbps with PRBS7 data pattern. Peaking frequency in the range of 1 to 6MHz.0.8dB
JPEAKJitter peakingMeasured at 25.78125Gbps with PRBS7 data pattern. Peaking frequency in the range of 1 to 17MHz.0.4dB
JPEAKJitter peakingMeasured at 28.4Gbps with PRBS7 data pattern. Peaking frequency in the range of 1 to 17MHz.0.4dB
BWPLLPLL bandwidthData rate of 10.3125Gbps with PRBS7 pattern5MHz
BWPLLPLL bandwidthData rate of 25.78125Gbps with PRBS7 pattern5.5MHz
BWPLLPLL bandwidthData rate of 28.4Gbps with PRBS7 pattern5MHz
JTOLInput jitter toleranceMeasured at 28.4Gbps with SJ frequency > 10MHz, 29dB input channel loss, PRBS31 data pattern, 800mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12.0.32UIpp
JTOLInput jitter toleranceMeasured at 25.78125Gbps with SJ frequency = 190 KHz, 30dB input channel loss, PRBS31 data pattern, 800mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12.9UIpp
JTOLInput jitter toleranceMeasured at 25.78125Gbps with SJ frequency = 940 KHz, 30dB input channel loss, PRBS31 data pattern, 800mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12.1UIpp
JTOLInput jitter toleranceMeasured at 25.78125Gbps with SJ frequency > 10MHz, 32dB input channel loss, PRBS31 data pattern, 800mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12.0.38UIpp
TEMPLOCK-CDR stay-in-lock ambient temperature range, negative ramp. Maximum temperature change below initial CDR lock acquisition temperature.85 °C starting ambient temperature, ramp rate -3 °C/minute, 1.7 liters/sec airflow, 12 layer PCB.115°C
TEMPLOCK+CDR stay-in-lock ambient temperature range, positive ramp. Maximum temperature change above initial CDR lock acquisition temperature.-40 °C starting ambient temperature, ramp rate +3 °C/minute, 1.7 liters/sec airflow, 12 layer PCB.125°C
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