The DS280DF810 has strong equalization capabilities that allow it to recover data over channels up to 35dB insertion loss (at 12.9GHz). As a result, the optimum placement for the DS280DF810 in a backplane and mid-plane application is with the higher-loss channel segment at the input and the lower-loss channel segment at the output. This reduces the equalization burden on the downstream ASIC/FPGA, as the DS280DF810 is equalizing a majority of the overall channel. This type of asymmetric placement is not a requirement, but when an asymmetric placement is required due to the presence of a passive backplane or mid-plane, then this becomes the recommended placement.

Figure 7-2 Backplane and Mid-Plane Application Block Diagram

Figure 7-3 Backplane and Mid-Plane Application Schematic