ZHCSKG3B September 2016 – February 2024 DS280DF810
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
The DS280DF810’s SMBus target address is strapped at power up using the ADDR[1:0] pins. The pin state is read on power up, after the internal power-on reset signal is de-asserted. The ADDR[1:0] pins are four-level LVCMOS IOs, which provides for 16 unique SMBus addresses. The four levels are achieved by pin strap options as follows:
| 8-BIT WRITE ADDRESS [HEX] | REQUIRED ADDRESS PIN STRAP VALUE | |
|---|---|---|
| ADDR1 | ADDR0 | |
| 0x30 | 0 | 0 |
| 0x32 | 0 | R |
| 0x34 | 0 | F |
| 0x36 | 0 | 1 |
| 0x38 | R | 0 |
| 0x3A | R | R |
| 0x3C | R | F |
| 0x3E | R | 1 |
| 0x40 | F | 0 |
| 0x42 | F | R |
| 0x44 | F | F |
| 0x46 | F | 1 |
| 0x48 | 1 | 0 |
| 0x4A | 1 | R |
| 0x4C | 1 | F |
| 0x4E | 1 | 1 |