The following example layout demonstrates how all signals can be escaped from the BGA array using microstrip routing on a generic 8+ layer stackup. This example layout assumes the following:

• Normal trace width: 0.27 mm (10.5 mil)
• Neck-down trace width: 0.18 mm (7 mil)
• Trace edge-to-edge spacing: 0.51 mm (20 mil)
• VIA finished hole size (diameter): 0.203 mm (8 mil)
• VIA-to-VIA spacing: 0.8 mm (31.5 mil)
• No VIA-in-pad used

Note that many other escape routing options exist using different trace width and spacing combinations. The optimum trace width and spacing will depend on the PCB material, PCB routing density, and other factors. Stripline escape routing is also possible and may be preferable in some application scenarios such as backplane applications.

Figure 11-5 Microstrip Example, Top Layer

Figure 11-7 Microstrip Example, Internal Signal Layer 2

Figure 11-6 Microstrip Example, Internal Signal Layer 1

Figure 11-8 Microstrip Example, Bottom Layer