ZHCSM45 june   2023 DS320PR1601

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Five-Level Control Inputs
      5. 7.3.5 Integrated Capacitors
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
  9. 8 Programming
    1. 8.1 Pin Configurations for Lanes
    2. 8.2 SMBUS/I2C Register Control Interface
      1. 8.2.1 Shared Registers
      2. 8.2.2 Channel Registers
    3. 8.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 PCIe x16 Lane Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

8.2 SMBUS/I2C Register Control Interface

If MODE = L2 (SMBus / I2C target control mode), the DS320PR1601 is configured through a standard I2C or SMBus interface that may operate up to 400 kHz. The device also can be configured through loading settings from EEPROM. The SMBus / I2C target address of the DS320PR1601 is determined by the pin strap settings on the xADDRx pins. Note addresses to access differential channels are different. To illustrate A_ADDR1_15_8 and A_ADDR0_15_8 sets the target address for bank of lanes 15-12 and 11-8 of Side A, while A_ADDR1_7_0 and A_ADDR0_7_0 sets for bank of lanes 7-4 and 3-0 of Side A. B side address is also set similarly. Table 8-2 provides SMBus / I2C target addresses.

Table 8-2 SMBus / I2C Target Address
x_ADDR1_x x_ADDR0_x

7-bit address

Upper (for Side A) / Lower (for Side B) 4 Lanes of each Bank

7-bit address

Lower (for Side A) / Upper (for Side B) 4 Lanes of each Bank
L0 L0 0x19 0x18
L0 L1 0x1B 0x1A
L0 L2 0x1D 0x1C
L0 L3 0x1F 0x1E
L0 L4 Reserved Reserved
L1 L0 0x21 0x20
L1 L1 0x23 0x22
L1 L2 0x25 0x24
L1 L3 0x27 0x26
L1 L4 Reserved Reserved
L2 L0 0x29 0x28
L2 L1 0x2B 0x2A
L2 L2 0x2D 0x2C
L2 L3 0x2F 0x2E
L2 L4 Reserved Reserved
L3 L0 0x31 0x30
L3 L1 0x33 0x32
L3 L2 0x35 0x34
L3 L3 0x37 0x36
L3 L4 Reserved Reserved

In SMBus/I2C modes the SCL, SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 10 pF.

Refer to the DS160PR1601 and DS320PR1601 Programming Guide for detail register sets and control configuration procedures.
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