As with any high-speed design, there are many factors which influence the overall performance. The following list indicates critical areas for consideration during design.

• Use 85 Ω impedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N traces should be done on the single-end segments of the differential pair.
• Use a uniform trace width and trace spacing for differential pairs.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias for a low inductance path for the return current.