In PCIe Gen 3.0, 4.0, and 5.0 applications, the specification requires Rx-Tx (of root-complex and endpoint) link training to establish and optimize signal conditioning settings at 8 Gbps, 16 Gbps, and 32 Gbps, respectively. In link training, the Rx partner requests a series of FIR – preshoot and de-emphasis coefficients (10 Presets) from the Tx partner. The Rx partner includes 7-levels of CTLE followed by a single tap DFE. The link training would pre-condition the signal, with an equalized link between the root-complex and endpoint resulting an optimized link. Note that there is no link training in PCIe Gen 1.0 (2.5 Gbps) or PCIe Gen 2.0 (5.0 Gbps) applications.

For operation in Gen 3.0, 4.0, and 5.0 links, the DS320PR810 is designed with linear data-path to pass the Tx Preset signaling (by root complex and end point) onto the Rx (of root complex and end point) for the PCIe Gen 3.0, 4.0, or 5.0 link to train and optimize the equalization settings. The linear redriver DS320PR810 helps extend the PCB trace reach distance by boosting the attenuated signals with its equalization, which allows the user to recover the signal by the downstream Rx more easily. The device must be placed in between the Tx and Rx (of root complex and end point) such a way that both Rx and Tx signal swing stays within the linearity range of the device. Adjustments to the DS320PR810 EQ setting should be performed based on the channel loss to optimize the eye opening in the Rx partner. The available EQ gain settings are provided in Table 7-1. For most PCIe systems the default flat gain setting 0 dB (GAIN = floating) would be sufficient. However, a flat gain attenuation can be utilized to apply extra equalization when needed to keep the data-path linear.

The DS320PR810 can be optimized for a given system utilizing its three configuration modes – Pin mode, SMBus/I²C Primary mode, and SMBus/I²C Secondary mode. In SMBus/I²C modes the SCL and SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩ is a good first approximation for a bus capacitance of 10 pF.

In PCIe applications PD0/1 pins can be connected to PCIe sideband signals PERST# with inverted polarity or one or more appropriate PRSNTx# signals to achieve desired RX detect functionality.

Figure 8-2 shows a simplified schematic for x16 lane configuration in Pin mode.

Figure 8-3 shows a simplified schematic for x16 lane configuration in SMBus/I²C Primary mode.

Figure 8-4 shows a simplified schematic for x16 lane configuration in SMBus/I²C Secondary mode.