ZHCSQD1 August 2022 DS320PR810
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Receiver | ||||||
| RLRX-DIFF | Input differential return loss | 50 MHz to 1.25 GHz | −22 | dB | ||
| 1.25 GHz to 2.5 GHz | −19 | dB | ||||
| 2.5 GHz to 4.0 GHz | −16 | dB | ||||
| 4.0 GHz to 8.0 GHz | −12 | dB | ||||
| 8.0 GHz to 16 GHz | −9 | dB | ||||
| RLRX-CM | Input common-mode return loss | 50 MHz to 2.5 GHz | −16 | dB | ||
| 2.5 GHz to 8.0 GHz | −9 | dB | ||||
| 8.0 GHz to 16 GHz | −6 | dB | ||||
| XTRX | Receiver-side pair-to-pair isolation; Port A or Port B | Minimum over 10 MHz to 16 GHz range | −40 | dB | ||
| Transmitter | ||||||
| VTX-AC-CM-PP | Tx AC Peak-to-Peak Common Mode Voltage | Measured with lowest EQ, GAIN = L4; PRBS-7, 32 Gbps, over at least 106 bits using a bandpass-Pass Filter from 30 Khz - 500 Mhz | 50 | mVpp | ||
| VTX-CM-DC-ACTIVE-IDLE-DELTA | Absolute Delta of DC Common Mode Voltage during L0 and Electrical Idle | VTX-CM-DC = |VOUTn+ + VOUTn–|/2, Measured by taking the absolute difference of VTX-CM-DC during PCIe state L0 and Electrical Idle | 0 | 120 | mV | |
| VTX-RCV-DETECT | Amount of Voltage change allowed during Receiver Detection | Measured while Tx is sensing whether a low-impedance Receiver is present. No load is connected to the driver output | 0 | 600 | mV | |
| RLTX-DIFF | Output differential return loss | 50 MHz to 1.25 GHz | −22 | dB | ||
| 1.25 GHz to 2.5 GHz | −21 | dB | ||||
| 2.5 GHz to 4.0 GHz | −19 | dB | ||||
| 4.0 GHz to 8.0 GHz | −14 | dB | ||||
| 8.0 Ghz to 16 Ghz | −10 | dB | ||||
| RLTX-CM | Output Common-mode return loss | 50 MHz to 2.5 GHz | −14 | dB | ||
| 2.5 GHz to 8.0 GHz | −10 | dB | ||||
| 8.0 GHz to 16 GHz | −7 | dB | ||||
| XTTX | Transmit-side pair-to-pair isolation | Minimum over 10 MHz to 16 GHz range | −40 | dB | ||
| Device Datapath | ||||||
| TPLHD/PHLD | Input-to-output latency (propagation delay) through a data channel | For either Low-to-High or High-to-Low transition. | 100 | 140 | ps | |
| LTX-SKEW | Lane-to-Lane Output Skew | Between any two lanes within a single transmitter. | 20 | ps | ||
| TRJ-DATA | Additive Random Jitter with data | Jitter through redriver minus the calibration trace. 32 Gbps PRBS15. 800 mVpp-diff input swing. | 75 | fs | ||
| TRJ-INTRINSIC | Intrinsic additive Random Jitter with clock | Jitter through redriver minus the calibration trace. 16 Ghz CK. 800 mVpp-diff input swing. | 40 | fs | ||
| JITTERTOTAL-DATA | Additive Total Jitter with data | Jitter through redriver minus the calibration trace. 32 Gbps PRBS15. 800 mVpp-diff input swing. | 1.5 | ps | ||
| JITTERTOTAL-INTRINSIC | Intrinsic additive Total Jitter with clock | Jitter through redriver minus the calibration trace. 16 Ghz CK. 800 mVpp-diff input swing. | 1.7 | ps | ||
| FLAT-GAIN | Broadband DC and AC flat gain - input to output, measured at DC | Minimum EQ, GAIN1/0 = L0 | −5.6 | dB | ||
| Minimum EQ, GAIN1/0 = L1 | −3.8 | dB | ||||
| Minimum EQ, GAIN1/0 = L2 | −1.2 | dB | ||||
| Minimum EQ, GAIN1/0 = L3 | 2.6 | dB | ||||
| Minimum EQ, GAIN1/0 = L4 (Float) | 0.6 | dB | ||||
| EQ-MAX16G | EQ boost at max setting (EQ INDEX = 19) | AC gain at 16 GHz relative to gain at 100 MHz. | 22 | dB | ||
| FLAT-GAINVAR | Flat gain variation across PVT measured at DC | GAIN1/0 = L4, minimum EQ setting. Max-Min. | −2.5 | 1.5 | dB | |
| EQ-GAINVAR | EQ boost variation across PVT | At 16 Ghz. GAIN1/0 = L4, maximum EQ setting. Max-Min. | −3.0 | 4.0 | dB | |
| LINEARITY-DC | Output DC Linearity | at GAIN1/0 = L4 | 1700 | mVpp | ||
| LINEARITY-AC | Output AC Linearity at 32Gbps | at GAIN1/0 = L4 | 700 | mVpp | ||