ZHCSO34F April   2011  – August 2021 DS80PCI402

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1) (1) (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics — Serial Management Bus Interface
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 15
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBUS Mode
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer of Data Through the SMBus
      3. 8.5.3 Writing a Register
      4. 8.5.4 Reading a Register
      5. 8.5.5 SMBus Controller Mode
    6. 8.6 Register Maps
      1.      31
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Considerations for Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PD Power Dissipation VDD = 2.5 V supply,
EQ Enabled,
VOD = 1.0 Vp-p,
RXDET = 1, PRSNT = 0		 500 700 mW
VIN = 3.3 V supply,
EQ Enabled,
VOD = 1.0 Vp-p,
RXDET = 1, PRSNT = 0		 660 900 mW
LVCMOS / LVTTL DC SPECIFICATIONS
VIH25 High-level input voltage
( PRSNT, READ_EN pins)		 2.5 V mode 2.0 VDD V
VIH33 High-level input voltage
( PRSNT, READ_EN pins)		 3.3 V mode 2.0 VIN V
VIL Low-Level Input Voltage
( PRSNT, READ_EN pins)		 0 0.8 V
VOH High-level output voltage
( ALL_DONE pin)		 IOH = −4 mA 2.0 V
VOL Low-level output voltage
( ALL_DONE pin)		 IOL = 4 mA 0.4 V
IIH Input high current ( PRSNT pin) VIN = 3.6 V,
LVCMOS = 3.6 V		 –15 15 μA
Input high current with internal resistors (4–level input pin) 20 150 μA
IIL Input low current ( PRSNT pin) VIN = 3.6 V,
LVCMOS = 0 V		 –15 15 μA
Input low current with internal resistors (4-level input pin) –160 –40 μA
CML RECEIVER INPUTS (IN_n+, IN_n-)
RLRX-DIFF RX differential return loss 0.05 to 1.25 GHz –16 dB
1.25 to 2.5 GHz –16 dB
2.5 to 4.0 GHz –14 dB
RLRX-CM RX common mode return loss 0.05 to 2.5 GHz –12 dB
2.5 to 4.0 GHz –8 dB
ZRX-DC RX DC single-ended impedance Tested at VDD = 2.5 V 40 50 60 Ω
ZRX-DIFF-DC RX DC differential mode impedance Tested at VDD = 2.5 V 80 100 120 Ω
ZRX-HIGH-IMP-DC-POS DC input common mode impedance for V > 0 VID = 0 to 200 mV,
ENSMB = 0, RXDET = 0,
VDD = 2.5 V		 50 kΩ
VRX-DIFF-DC Differential RX peak-to-peak voltage (VID) Tested at pins 1.2 V
VRX-SIGNAL-DET-DIFF-PP Signal detect assert level for active data signal SD_TH = float,
0101 pattern at 8 Gbps
Measured at pins		 180 mVp-p
VRX-IDLE-DET-DIFF-PP Signal detect deassert level for electrical idle SD_TH = float,
0101 pattern at 8 Gbps
Measured at pins		 110 mVp-p
HIGH-SPEED OUTPUTS
VTX-DIFF-PP Output voltage differential swing Differential measurement with OUT_n+ and OUT_n-,
terminated by 50Ω to GND,
AC-Coupled, VID = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0(1)		 0.8 1.0 1.2 Vp-p
VTX-DE-RATIO_3.5 TX de-emphasis ratio VOD = 1.0 Vp-p,
DEM0 = 0, DEM1 = R
Gen 1 & 2 modes only		 –3.5 dB
VTX-DE-RATIO_6 TX de-emphasis ratio VOD = 1.0 Vp-p,
DEM0 = R, DEM1 = R
Gen 1 & 2 modes only		 –6 dB
TTX-DJ Deterministic Jitter VID = 800 mV, PRBS15 pattern, 8.0 Gbps, VOD = 1.0 V,
EQ = 00, DE = 0 dB (no input or output trace loss)		 0.05 UIpp
TTX-RJ Random Jitter VID = 800 mV, 0101 pattern, 8.0 Gbps, VOD = 1.0 V,
EQ = 00, DE = 0 dB, (no input or output trace loss)		 0.3 ps RMS
TTX-RISE-FALL TX rise/fall time 20% to 80% of differential output voltage(3) 35 45 ps
TRF-MISMATCH TX rise/fall mismatch 20% to 80% of differential output voltage(3) 0.01 0.1 UI
RLTX-DIFF TX differential return loss 0.05 to 1.25 GHz –16 dB
1.25 to 2.5 GHz –12 dB
2.5 to 4 GHz –11 dB
RLTX-CM TX common mode return loss 0.05 to 2.5 GHz –12 dB
2.5 to 4 GHz –8 dB
ZTX-DIFF-DC DC differential TX impedance 100 Ω
VTX-CM-AC-PP TX AC peak-peak common mode voltage VOD = 1.0 Vp-p,
DEM0 = 1, DEM1 = 0(3)		 100 mVp-p
ITX-SHORT TX short circuit current limit Total current the transmitter can supply when shorted to VDD or GND 20 mA
VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute delta of DC common mode voltage during L0 and electrical idle (3) 100 mV
VTX-CM-DC-LINE-DELTA Absolute delta of DC common mode voltgae between TX+ and TX- (3) 25 mV
TTX-IDLE-DATA Max time to transition to differential DATA signal after IDLE VID = 1.0 Vp-p, 8 Gbps 3.5 ns
TTX-DATA-IDLE Max time to transition to IDLE after differential DATA signal VID = 1.0 Vp-p, 8 Gbps 6.2 ns
TPLHD/PHLD High-to-low and low-to-high differential propagation delay EQ = 00(2) 200 ps
TLSK Lane-to-lane skew T = 25° C, VDD = 2.5 V 25 ps
TPPSK Part-to-part propagation delay skew T = 25° C, VDD = 2.5 V 40 ps
EQUALIZATION
DJE1 Residual deterministic jitter at
8 Gbps		 35” 4mils FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 0x1F,
DEM = 0 dB		 0.14 UIpp
DJE2 Residual deterministic jitter at
5 Gbps		 35” 4mils FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 0x1F,
DEM = 0 dB		 0.1 UIpp
DJE3 Residual deterministic jitter at 2.5 Gbps 35” 4mils FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 0x1F,
DEM = 0 dB		 0.05 UIpp
DJE4 Residual deterministic jitter at
8 Gbps		 10 meters 30-awg cable,
VID = 0.8 Vp-p,
PRBS15, EQ = 0x2F,
DEM = 0 dB		 0.16 UIpp
DJE5 Residual deterministic jitter at
5 Gbps		 10 meters 30-awg cable,
VID = 0.8 Vp-p,
PRBS15, EQ = 0x2F,
DEM = 0 dB		 0.1 UIpp
DJE6 Residual deterministic jitter at 2.5 Gbps 10 meters 30-awg cable,
VID = 0.8 Vp-p,
PRBS15, EQ = 0x2F,
DEM = 0 dB		 0.05 UIpp
DE-EMPHASIS (GEN 1,2 MODE ONLY)
DJD1 Residual deterministic jitter at 2.5 Gbps and 5.0 Gbps 10” 4mils FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 00,
VOD = 1.0 Vp-p,
DEM = −3.5 dB		 0.1 UIpp
DJD2 Residual deterministic jitter at 2.5 Gbps and 5.0 Gbps 20” 4mils FR4,
VID = 0.8 Vp-p,
PRBS15, EQ = 00,
VOD = 1.0 Vp-p,
DEM = –9 dB		 0.1 UIpp
(1) In GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output VOD level set by DEMA/B[1:0] in GEN3 mode is dependent on the VID level and the frequency content. The DS80PCI402 repeater in GEN3 mode is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support the PCIe GEN3 handshake negotiation link training.
(2) Propagation delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the largest propagation delays.
(3) Parameter is characterized but not tested in production.
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