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ZHCSO34F April 2011 – August 2021 DS80PCI402

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6.6 Electrical Characteristics — Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
V_IL	Data, clock input low voltage				0.8	V
V_IH	Data, clock input high voltage		2.1		3.6	V
I_PULLUP	Current through pullup resistor or current source	High Power Specification	4			mA
V_DD	Nominal bus voltage		2.375		3.6	V
I_LEAK-Bus	Input leakage per bus segment	⁽¹⁾	-200		+200	µA
I_LEAK-Pin	Input leakage per device pin			-15		µA
C_I	Capacitance for SDA and SCL	⁽¹⁾ ⁽²⁾			10	pF
R_TERM	External termination resistance pull to V_DD = 2.5 V ± 5% OR 3.3 V ± 10%	Pullup V_DD = 3.3 V, ⁽¹⁾⁽²⁾⁽³⁾		2000		Ω
R_TERM		Pullup V_DD = 2.5 V, ⁽¹⁾⁽²⁾⁽³⁾		1000		Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB	Bus operating frequency	ENSMB = VDD (Reader mode)			400	kHz
FSMB	Bus operating frequency	ENSMB = FLOAT (Controller mode)	280	400	520	kHz
T_BUF	Bus free time between stop and start condition		1.3			µs
T_HD:STA	Hold time after (repeated) start condition. After this period, the first clock is generated.	At I_PULLUP, Max	0.6			µs
T_SU:STA	Repeated start condition setup time		0.6			µs
T_SU:STO	Stop condition setup time		0.6			µs
T_HD:DAT	Data hold time		0			ns
T_SU:DAT	Data setup time		100			ns
T_LOW	Clock low period		1.3			µs
T_HIGH	Clock high period	⁽⁴⁾	0.6		50	µs
t_F	Clock/data fall time	⁽⁴⁾			300	ns
t_R	Clock/data rise time	⁽⁴⁾			300	ns
t_POR	Time in which a device must be operational after power-on reset	⁽⁴⁾ ⁽⁵⁾			500	ms

(1) Recommended value.

(2) Recommended maximum capacitance load per bus segment is 400 pF.

(3) Maximum termination voltage should be identical to the device supply voltage.

(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common AC specifications for details.

(5) Specified by Design. Parameter not tested in production.