ZHCSO34F April 2011 – August 2021 DS80PCI402
PRODUCTION DATA
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1 kΩ to VDD to enable SMBus Reader MODE and allow access to the configuration registers.
The DS80PCI402 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS reader address inputs. The AD[3:0] pins have internal pulldown. When left floating or pulled low the AD[3:0] = 0000'b, the device default address byte is 0xB0. Based on the SMBus 2.0 specification, the DS80PCI402 has a 7-bit reader address. The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the AD[3:0] inputs. Below are the 16 addresses.
| AD[3:0] SETTINGS | ADDRESS BYTES (HEX) | 7-BIT reader ADDRESS (HEX) |
|---|---|---|
| 0000 | B0 | 58 |
| 0001 | B2 | 59 |
| 0010 | B4 | 5A |
| 0011 | B6 | 5B |
| 0100 | B8 | 5C |
| 0101 | BA | 5D |
| 0110 | BC | 5E |
| 0111 | BE | 5F |
| 1000 | C0 | 60 |
| 1001 | C2 | 61 |
| 1010 | C4 | 62 |
| 1011 | C6 | 63 |
| 1100 | C8 | 64 |
| 1101 | CA | 65 |
| 1110 | CC | 66 |
| 1111 | CE | 67 |
The SDA/SCL pins are 3.3 V tolerant, but are not 5 V tolerant. An external pullup resistor is required on the SDA and SCL line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading, and speed.