When MODE0 is HIGH, data from IN_[27:21], IN_[17:0], HS, VS and DE is serialized and driven out on OA_[3:0]+/- and OB_[3:0]+/- with OA_C+/- and OB_C+/-. The input LVCMOS data is split into odd and even pixels starting with the odd (first) pixel outputs OA_[3:0]+/- and then the even (second) pixel outputs OB_[3:0]+/-. The splitting of the data signals starts with DE (data enable) transitioning from logic LOW to HIGH indicating active data (see Figure 7-10). The number of clock cycles during blanking must be an EVEN number. This configuration will allow the user to interface with two FPD-Link receivers or other dual pixel inputs.

In this configuration IN_CLK can range from 50 MHz to 185 MHz, resulting in a total maximum payload of 1.4 Gbps (28 bits * 50 MHz) to 5.18 Gbps (28 bits * 185 MHz). Each LVDS driver will operate at a speed of 7 bits per 2 input clock cycles, resulting in a serial line rate of 175 Mbps to 647.5 Mbps. OA_C+/- and OA_B+/- will operate at ½ the rate as IN_CLK with a duty cycle ratio of 57:43.

In the Single Pixel Input / Dual Pixel Output mode OA_x and OB_x can become misaligned if the clock or data is interrupted or PDB is toggled. If the clock or data is interrupted or PDB is toggled to prevent misalignment the following should be done:

1. Disable the clock and data.
2. Toggle PDB to Low and then High.
3. After PDB settles reset the data pattern and enable the clock and data.