Refer to the AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.

• Use 100-Ω coupled differential pairs
• Use differential connectors when above 500 Mbps
• Minimize skew within the pair
• Use the S/2S/3S rule in spacings
  • S = space between the pairs
  • 2S = space between pairs
  • 3S = space to LVCMOS signals
• Place ground vias next to signal vias when changing between layers
• When a signal changes reference planes, place a bypass cap and vias between the new and old reference plane

For more tips and detailed suggestions regarding high speed board layout principles, see the LVDS Owner's Manual at http://www.ti.com/lvds