When MODE0 is set to low, data from IN_[27:21], IN_[17:0], HS, VS and DE is serialized and driven out on OA_[3:0]+/- with OA_C+/-.

In this configuration IN_CLK can range from 25 MHz to 105 MHz, resulting in a total maximum payload of 700 Mbps (28 bits * 25MHz) to 2.94 Gbps (28 bits * 105 MHz). Each LVDS driver will operate at a speed of 7 bits per input clock cycle, resulting in a serial line rate of 175 Mbps to 735 Mbps. OA_C+/- will operate at the same rate as IN_CLK with a duty cycle ratio of 57:43.