ZHCSI69B june   2018  – september 2020 DS90C189-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Typical Application Diagrams
  6. Revision History
  7. Pin Configuration and Functions
    1.     DS90C189 Pin Descriptions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended Input Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 AC Timing Diagrams
    9. 7.9 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 AEC-Q100 Qualified
      2. 8.3.2 ESD Protection
      3. 8.3.3 Operating Modes
      4. 8.3.4 LVDS Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 Single Pixel Input / Single Pixel Output
      3. 8.4.3 Single Pixel Input / Dual Pixel Output
      4. 8.4.4 Pixel Clock Edge Select (RFB)
      5. 8.4.5 Power Management
      6. 8.4.6 Sleep Mode (PDB)
      7. 8.4.7 LVDS Outputs
      8. 8.4.8 LVCMOS Inputs
    5. 8.5 Programming
      1. 8.5.1 LVDS Interface / TFT Color Data Recommended Mapping
        1. 8.5.1.1 Color Mapping Information
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LVDS Interconnect Guidelines
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Up Sequence
    2. 10.2 Power Supply Filtering
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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Power Up Sequence

The VDD power supply ramp should start from GND +/-5mV and ramp monotonically to the recommended supply voltage. The VDD power supply pins do not require a specific power on sequence and can be powered on in any order. However, the PDB pin should only be set to logic HIGH once the power sent to all supply pins is stable. Active data inputs should not be applied to the DS90C189-Q1 until all of the input power pins have been powered on, settled to the recommended operating voltage and the PDB pin has be set to logic HIGH.

The user experience can be impacted by the way a system powers up and powers down an LCD screen. The following sequence is recommended:

Power up sequence (DS90C189-Q1 PDB input initially LOW):

  1. Ensure that all supply pins are at GND +/-5mV

  2. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
  3. Toggle DS90C189-Q1 power down pin to PDB = VDD.
  4. Enable clock and wait for additional 0-200ms to ensure display noise won’t occur.
  5. Enable video source output; start sending black video data.
  6. Send >1ms of black video data; this allows the DS90C189-Q1 to be phase locked, and the display to show black data first.
  7. Start sending true image data.
  8. Enable backlight.

Power Down sequence (DS90C189-Q1 PDB input initially HIGH):

  1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
  2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive this for >2 frame times.
  3. Set DS90C189-Q1 power down pin to PDB = GND.
  4. Disable the video output of the video source.
  5. Remove power from the LCD panel for lowest system power.
  6. Ensure that VDD supply discharges to GND +/- 5mV before starting the next power up sequence. If rapid power off/on system behavior is required, then it is recommended to utilize a discharge circuit to ensure VDD returns to GND +/- 5mV between power off/on conditions