SNLS043H May   2000  – January 2016 DS90CR216A , DS90CR286A , DS90CR286A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics: Receiver
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 LVDS Receivers
        1. 7.3.1.1 LVDS Input Termination
      2. 7.3.2 Phase Locked Loop (PLL)
      3. 7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
      4. 7.3.4 LVCMOS Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Cables
        2. 8.2.2.2 Bit Resolution and Operating Frequency Compatibility
        3. 8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
        4. 8.2.2.4 RSKM Interoperability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DGG Package
56-Pin TSSOP
DS90CR286A Top View
DS90CR216A DS90CR286A DS90CR286A-Q1 01291022.png
DGG Package
48-Pin TSSOP
DS90CR216A Top View
DS90CR216A DS90CR286A DS90CR286A-Q1 10087313.png

DS90CR286A Pin Functions — DGG0056A Package — 28-Bit Channel Link Receiver

PIN I/O , TYPE PIN DESCRIPTION
NAME NO.
RxIN0+, RxIN0-,
RxIN1+, RxIN1-,
RxIN2+, RxIN2-,
RxIN3+, RxIN3-		 10, 9,
12, 11,
16, 15,
20, 19		 I, LVDS Positive and negative LVDS differential data inputs. 100-Ω termination resistors should be placed between RxIN+ and RxIN- receiver inputs as close as possible to the receiver pins for proper signaling.
RxCLKIN+,
RxCLKIN-		 18,
17		 I, LVDS Positive and negative LVDS differentiaI clock input. 100-Ω termination resistor should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close as possible to the receiver pins for proper signaling.
RxOUT[27:0] 7, 6, 5, 3,
2, 1, 55, 54,
53, 51, 50, 49,
47, 46, 45, 43,
42, 41, 39, 38,
37, 35, 34, 33,
32, 30, 29, 27		 O, LVCMOS LVCMOS level data outputs.
RxCLK OUT 26 O, LVCMOS LVCMOS Ievel clock output. The rising edge acts as the data strobe.
PWR DWN 25 I, LVCMOS LVCMOS level input. When asserted low, the receiver outputs are low.
VCC 56, 48, 40, 31 Power Power supply pins for LVCMOS outputs.
GND 52, 44, 36,
28, 4		 Power Ground pins for LVCMOS outputs.
PLL VCC 23 Power Power supply for PLL.
PLL GND 24, 22 Power Ground pin for PLL.
LVDS VCC 13 Power Power supply pin for LVDS inputs.
LVDS GND 21, 14, 8 Power Ground pins for LVDS inputs.

DS90CR216A Pin Functions — DGG0048A Package — 21-Bit Channel Link Receiver

PIN I/O , TYPE PIN DESCRIPTION
NAME NO.
RxIN0+, RxIN0-,
RxIN1+, RxIN1-,
RxIN2+, RxIN2-		 9, 8,
11, 10,
15, 14		 I, LVDS Positive and negative LVDS differential data inputs. 100-Ω termination resistors should be placed between RxIN+ and RxIN- receiver inputs as close as possible to the receiver pins for proper signaling.
RxCLKIN+,
RxCLKIN-		 17,
16		 I, LVDS Positive and negative LVDS differentiaI clock input. 100-Ω termination resistor should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close as possible to the receiver pins for proper signaling.
RxOUT[20:0] 5, 4, 2, 1, 47,
46, 45, 43, 41,
40, 39, 37, 35,
34, 33, 31, 30,
29, 27, 26, 24		 O, LVCMOS LVCMOS level data outputs.
RxCLK OUT 23 O, LVCMOS LVCMOS Ievel clock output. The rising edge acts as the data strobe.
PWR DWN 22 I, LVCMOS LVCMOS level input. When asserted low, the receiver outputs are low.
VCC 48, 42, 36, 28 Power Power supply pins for LVCMOS outputs.
GND 44, 38, 32,
25, 3		 Power Ground pins for LVCMOS outputs.
PLL VCC 20 Power Power supply for PLL.
PLL GND 21, 19 Power Ground pin for PLL.
LVDS VCC 12 Power Power supply pin for LVDS inputs.
LVDS GND 18, 13, 7 Power Ground pins for LVDS inputs.
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