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SNLS026D March 2000 – June 2016 DS90LV027A

PRODUCTION DATA.

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- MSOI002K

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage, V_CC		–0.3	4	V
Input voltage, DI		–0.3	3.6	V
Output voltage, DO±		–0.3	3.9	V
Maximum package power dissipation at 25°C	D package		1190	mW
Maximum package power dissipation at 25°C	Derate D package		9.5 mW/°C above 25°C	°C
Lead temperature range, soldering (4 s)			260	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±8000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000
		EIAJ, 0 Ω, 200 pF	±1000
		IEC direct, 330 Ω, 150 pF	±4000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	Supply voltage	3	3.3	3.6	V
T_A	Operating free-air temperature	–40	25	85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾			DS90LV027A	UNIT
			D (SOIC)
			8 PINS
R_θJA	Junction-to-ambient thermal resistance	Low-K thermal resistance⁽²⁾	212	°C/W
R_θJA	Junction-to-ambient thermal resistance	High-K thermal resistance⁽²⁾	112	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance		69.1	°C/W
R_θJB	Junction-to-board thermal resistance		47.7	°C/W
ψ_JT	Junction-to-top characterization parameter		15.2	°C/W
ψ_JB	Junction-to-board characterization parameter		47.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance		—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽³⁾

PARAMETER		TEST CONDITIONS		MIN	TYP⁽²⁾	MAX	UNIT
V_OD	Output differential voltage	R_L = 100 Ω (see Figure 15), DO+, DO− pins		250	360	450	mV
ΔV_OD	V_OD magnitude change	R_L = 100 Ω (see Figure 15), DO+, DO− pins			1	35	mV
V_OH	Output high voltage	R_L = 100 Ω (see Figure 15), DO+, DO− pins			1.4	1.6	V
V_OL	Output low voltage	R_L = 100 Ω (see Figure 15), DO+, DO− pins		0.9	1.1		V
V_OS	Offset voltage	R_L = 100 Ω (see Figure 15), DO+, DO− pins		1.125	1.2	1.375	V
ΔV_OS	Offset magnitude change	R_L = 100 Ω (see Figure 15), DO+, DO− pins		0	3	25	mV
I_OXD	Power-off leakage	V_OUT = V_CC or GND, V_CC = 0 V, DO+, DO− pins			±1	±10	μA
I_OSD	Output short-circuit current	DO+, DO− pins			–5.7	–8	mA
V_IH	Input high voltage	DI pin		2		V_CC	V
V_IL	Input low voltage	DI pin		GND		0.8	V
I_IH	Input high current	V_IN = 3.3 V or 2.4 V, DI pin			±2	±10	μA
I_IL	Input low current	V_IN = GND or 0.5 V, DI pin			±1	±10	μA
V_CL	Input clamp voltage	I_CL = −18 mA, DI pin		–1.5	–0.6		V
I_CC	Power supply current	V_IN = V_CC or GND, V_CC pin	No load		8	14	mA
I_CC	Power supply current	V_IN = V_CC or GND, V_CC pin	R_L = 100 Ω		14	20	mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V_OD.

(2) All typicals are given for: V_CC = 3.3 V and T_A = 25°C.

(3) The DS90LV027A is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers outputs.

6.6 Switching Characteristics

R_L = 100 Ω and C_L = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		MIN	TYP⁽⁴⁾	MAX	UNIT
t_PHLD	Differential propagation delay high to low	0.3	0.8	1.5	ns
t_PLHD	Differential propagation delay low to high	0.3	1.1	1.5	ns
t_SKD1	Differential pulse skew \|t_PHLD − t_PLHD\|⁽⁵⁾	0	0.3	0.7	ns
t_SKD2	Channel to channel skew⁽⁶⁾	0	0.4	0.8	ns
t_SKD3	Differential part to part skew⁽⁷⁾	0		1	ns
t_SKD4	Differential part to part skew⁽⁸⁾	0		1.2	ns
t_TLH	Transition low to high time	0.2	0.5	1	ns
t_THL	Transition high to low time	0.2	0.5	1	ns
f_MAX	Maximum operating frequency⁽⁹⁾		350		MHz

(1) These parameters are ensured by design. The limits are based on statistical analysis of the device over PVT (process, voltage, temperature) ranges.

(2) C_L includes probe and fixture capacitance.

(3) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50 Ω, t_r ≤ 1 ns, t_f ≤ 1 ns (10%-90%).

(4) All typicals are given for: V_CC = 3.3 V and T_A = 25°C.

(5) t_SKD1, |t_PHLD − t_PLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel.

(6) t_SKD2 is the Differential Channel to Channel Skew of any event on the same device.

(7) t_SKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same V_CC and within 5°C of each other within the operating temperature range.

(8) t_SKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Max − Min| differential propagation delay.

(9) f_MAX generator input conditions: t_r = t_f < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%,
V_OD > 250 mV, all channels switching.