ZHCSJA9B September 2005 – January 2019 DS90LV028AH
PRODUCTION DATA.
The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to LVCMOS/LVTTL logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver inputs.
External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pullup and pulldown resistors should be in the 5-kΩ to 15-kΩ range to minimize loading and waveform distortion to the receiver. The common-mode bias point should be set to approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.
The DS90LV028AH is compliant to the original ANSI EIA/TIA-644 specification and is also compliant to the new ANSI EIA/TIA-644-A specification with the exception of the newly added ΔIIN specification. Due to the internal fail-safe circuitry, ΔIIN cannot meet the 6-µA maximum specified. This exception will not be relevant unless more than 10 receivers are used.
Additional information on the fail-safe biasing of LVDS devices may be found in AN-1194 Fail-Safe Biasing of LVDS Interfaces (SNLA051).