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SNLS011D July 1999 – August 2016 DS90LV032A

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PW|16
- MPDS361A
D|16
- MPDS178G

散热焊盘机械数据 (封装 | 引脚)

订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	V_CC	–0.3	4	V
Input voltage	R_IN+, R_IN–	–0.3	3.9	V
Enable input voltage	EN, EN*	–0.3	V_CC + 0.3	V
Output voltage	R_OUT	–0.3	V_CC + 0.3	V
Lead temperature, soldering (4 s)			260	°C
Maximum junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge⁽¹⁾	Human-body model (HBM)⁽¹⁾	±4500	V
V_(ESD)	Electrostatic discharge⁽¹⁾	Machine model (MM), EIAJ	±250	V

(1) ESD Ratings: HBM (1.5 kΩ, 100 pF) ≥ 4.5 kV and EIAJ (0 Ω, 200 pF) ≥ 250 V

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_CC	Supply voltage	3	3.3	3.6	V
	Receiver input voltage	GND		3	V
T_A	Operating free-air temperature	–40	25	85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DS90LV032A		UNIT
		PW (TSSOP)	D (SOIC)
		16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	110	75	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	47	36	°C/W
R_θJB	Junction-to-board thermal resistance	55	32	°C/W
ψ_JT	Junction-to-top characterization parameter	6	6	°C/W
ψ_JB	Junction-to-board characterization parameter	54	31.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over supply voltage and operating temperature ranges (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_TH	Differential input high threshold	V_CM = 1.2 V, R_IN+, R_IN– pin⁽²⁾			20	100	mV
V_TL	Differential input low threshold	V_CM = 1.2 V, R_IN+, R_IN– pin⁽²⁾		–100	–20		mV
VCMR	Common mode voltage range	VID = 200 mV peak to peak, R_IN+, R_IN– pin⁽³⁾		0.1		2.3	V
I_IN	Input current	V_CC = 3.6 V or 0 V, R_IN+, R_IN– pin	V_IN = 2.8 V	–10	±1	10	µA
		V_CC = 3.6 V or 0 V, R_IN+, R_IN– pin	V_IN = 0 V	–10	±1	10	µA
		V_CC = 0 V, V_IN = 3.6 V, R_IN+, R_IN– pin		–20		20	µA
V_OH	Output high voltage	I_OH = –0.4 mA, V_ID = 200 mV, R_OUT pin		2.7	3		V
		I_OH = –0.4 mA, input terminated, R_OUT pin		2.7	3		V
		I_OH = –0.4 mA, input shorted, R_OUT pin		2.7	3		V
V_OL	Output low voltage	I_OL = 2 mA, V_ID = –200 mV, R_OUT pin			0.1	0.25	V
I_OS	Output short-circuit current	Enabled, V_OUT = 0 V, R_OUT pin⁽⁴⁾		–15	–48	–120	mA
I_OZ	Output TRI-STATE current	Disabled, V_OUT = 0 V or V_CC		–10	±1	10	µA
V_IH	Input high voltage	EN, EN* pins		2		V_CC	V
V_IL	Input low voltage	EN, EN* pins		GND		0.8	V
I_I	Input current	V_IN = 0 V or V_CC, other input = V_CC or GND, EN, EN* pins		–10	±1	10	µA
V_CL	Input clamp voltage	I_CL = –18 mA, EN, EN* pins		–1.5	–0.8		V
I_CC	No load supply current	EN, EN* = V_CC or GND, inputs open, V_CC pin			10	15	mA
I_CC	Receivers enabled	EN, EN* = 2.4 V or 0.5 V, inputs open, V_CC pin			10	15	mA
I_CCZ	No load supply current	Receivers disabled, EN = GND, EN* = V_CC, inputs open, V_CC pin			3	5	mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified.

(2) V_CC is always higher than R_IN+ and R_IN– voltage. R_IN– and R_IN+ are allowed to have a voltage range –0.2 V to V_CC – VID / 2. However, to be compliant with AC specifications, the common voltage range is 0.1 V to 2.3 V

(3) The VCMR range is reduced for larger VID. Example: if VID = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs shorted is valid over a common mode range of 0 V to 2.3 V. A VID up to V_CC – 0 V may be applied to the R_IN+/ R_IN– inputs with the common mode voltage set to V_CC / 2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew specifications apply for 200 mV ≤ VID ≤ 800 mV over the common mode range.

(4) Output short-circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only. Only one output must be shorted at a time, do not exceed maximum junction temperature specification.

6.6 Switching Characteristics

over supply voltage and operating temperature ranges (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
t_PHLD	Differential propagation delay, high to low	C_L = 10 pF	1.8		3.3	ns
t_PLHD	Differential propagation delay, low to high	V_ID = 200 mV	1.8		3.3	ns
t_SKD1	Differential pulse skew⁽³⁾ \|t_PHLD – t_PLHD\|	See Figure 4 and Figure 5	0	0.1	0.35	ns
t_SKD2	Differential channel-to-channel skew⁽⁴⁾	Same device	0	0.1	0.5	ns
t_SKD3	Differential part-to-part skew⁽⁵⁾				1	ns
t_SKD4	Differential part-to-part skew⁽⁶⁾				1.5	ns
t_TLH	Rise time			0.35	1.2	ns
t_THL	Fall time			0.35	1.2	ns
t_PHZ	Disable time high to Z	R_L = 2 kΩ		8	12	ns
t_PLZ	Disable time low to Z	C_L = 10 pF		6	12	ns
t_PZH	Enable time Z to high	See Figure 6 and Figure 7		11	17	ns
t_PZL	Enable time Z to low			11	17	ns
f_MAX	Maximum operating frequency⁽⁷⁾	All channels switching	200	250		MHz

(1) All typicals are given for: V_CC = 3.3 V, T_A = 25°C.

(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50 Ω, t_r and t_f (0% to 100%) ≤ 3 ns for R_IN.

(3) t_SKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel

(4) t_SKD2, channel-to-channel skew, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs.

(5) t_SKD3, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V_CC, and within 5°C of each other within the operating temperature range.

(6) t_SKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Maximum – Minimum| differential propagation delay.

(7) f_MAX generator input conditions: t_r = t_f < 1 ns (0% to 100%), 50% duty cycle, differential (1.05-V to 1.35-V peak-to-peak). Output criteria: 60% / 40% duty cycle, V_OL (maximum: 0.4 V), V_OH (minimum: 2.7 V), load = 10 pF (stray plus probes).

6.7 Dissipation Ratings

	MAXIMUM PACKAGE POWER DISSIPATION AT 25°C
D package	1025 mW
PW package	866 mW
Derate D package	8.2 mW/°C above 25°C
Derate PW package	6.9 mW/°C above 25°C

6.8 Typical Characteristics

Figure 1. Typical Pulse Skew Variation
vs Common Mode Voltage

Figure 3. Variation in Low-to-High Propagation Delay vs VCM

Figure 2. Variation in High-to-Low Propagation Delay
vs VCM