ZHCSMR3A november 2020 – november 2020 DS90UB633A-Q1
PRODUCTION DATA
The I2C-compatible interface allows programming of the DS90UB633A-Q1, DS90UB662-Q1, or an external remote device (such as image sensor) through the bidirectional control channel. Register programming transactions to/from the DS90UB633A/662 chipset are employed through the clock (SCL) and data (SDA) lines. These two signals have open drain I/Os, and both lines must be pulled up to V(VDDIO) by an external resistor. Pullup resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by releasing the output and allowing it to be pulled up externally. The appropriate pullup resistor values depend upon the total bus capacitance and operating speed. The DS90UB633A-Q1 I2C bus data rate supports up to 400 kbps according to I2C fast mode specifications.
For further description of general I2C communication, refer to the Understanding the I2C Bus application note . For more information on choosing appropriate pullup resistor values, see the I2C Bus Pullup Resistor Calculation application note .