The chipset provides error detection operations for validating data integrity in long distance transmission and reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data transmission error checking. The error detection operating modes support data validation of the following signals:

• Bidirectional control channel data across the serial link
• Parallel video/sync data across the serial link

The chipset provides 1 parity bit on the forward channel and 4 cyclic redundancy check (CRC) bits on the back channel for error detection purposes. The DS90UB633A/662 chipset checks the forward and back channel serial links for errors and stores the number of detected errors in two 8-bit registers in the serializer and the deserializer, respectively.

To check parity errors on the forward channel, monitor registers 0x55 and 0x56 on the DS90UB662. The parity error counter registers return the number of data parity errors that have been detected on the FPD3 receiver data since the last detection of valid lock or last read of these registers (0x55 and 0x56). These registers are cleared on read.

To check CRC errors on the back channel, monitor registers 0x0A and 0x0B on the serializer.