Design circuit board layout and stack-up for the serializer/deserializer devices to provide low-noise power feed to the device. Good layout practice also separates high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, making the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of the tantalum capacitors should be at least 5× the power supply voltage being used.

TI recommends surface mount capacitors due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50-µF to 100-µF range and smooths low frequency switching noise. TI recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor increases the inductance of the path.

A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency.

Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.

Use at least a four-layer board with a power and ground plane. Locate LVCMOS signals away from the differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential lines of 100 Ω are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise appears as common-mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.

Information on the WQFN package is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

Ground

TI recommends that a consistent ground plane reference for the high-speed signals in the PCB design to provide the best image plane for signal traces running parallel to the plane. Connect the thermal pad of the DS90UB633A-Q1 to the GND plane with vias.

Routing FPD-Link III Signal Traces and PoC Filter

Routing the FPD-Link III signal traces between the RIN pins and the connector as well as connecting the PoC filter to these traces are the most critical pieces of a successful DS90UB633A-Q1 PCB layout. Figure 10-2 shows an example PCB layout of the DS90UB633A-Q1 configured for interface to remote sensor modules over coaxial cables. The layout example also uses a footprint of an edge-mount FAKRA connector provided by Rosenberger (P/N: 59S20X-40ML5-Z).

The following list provides essential recommendations for routing the FPD-Link III signal traces between the DS90UB633A-Q1 receiver output pins (DOUT) and the FAKRA connector, and connecting the PoC filter.

• The routing of the FPD-Link III traces may be all on the top layer (as shown in the example) or partially embedded in middle layers if EMI is a concern
• The AC-coupling capacitors should be on the top layer and very close to the DS90UB633A-Q1 output pins to minimize the length of coupled differential trace pair between the pins and the capacitors
• Route the DOUT+ trace between the AC-coupling capacitor and the FAKRA connector as a 50-Ω single-ended micro-strip with tight impedance control (±10%). Calculate the proper width of the trace for a 50-Ω impedance based on the PCB stack-up. Ensure that the trace can carry the PoC current for the maximum load presented by the remote sensor module.
• The PoC filter should be connected to the ROUT+ trace through the first ferrite bead (FB1 ). The FB1 should be touching the high-speed trace to minimize the stub length seen by the transmission line. Create an anti-pad or a moat under the FB1 pad that touches the trace. The anti-pad should be a plane cutout of the ground plane directly underneath the top layer without cutting out the ground reference under the trace. The purpose of the anti-pad is to maintain the impedance as close to 50 Ω as possible.
• Route the DOUT– trace loosely coupled to the DOUT+ trace for the length similar to the DOUT+ trace length when possible. This will help the differential nature of the receiver to cancel out any common-mode noise that may be present in the environment that may couple on to the DOUT+ and DOUT– signal traces. When routing on inner layers, length matching for single-ended traces does not provide as significant benefit.

When configured for STP and routing differential signals to the DS90UB633A-Q1 receiver inputs, the traces should maintain 100-Ω differential impedance routed to the connector. When choosing to implement a common mode choke for common mode noise reduction, take care to minimize the effect of any mismatch. Figure 60 shows an example PCB layout for STP configuration.