The DS90UB633A-Q1 is optimized to interface with the DS90UB662-Q1 using a 50-Ω coax interface. The DS90UB633A-Q1 also works with the DS90UB662-Q1 using an STP interface.

The DS90UB633A/662 FPD-Link III chipsets are intended to link mega-pixel camera imagers and video processors in ECUs. The Serializer/Deserializer chipset can operate from 56.25 MHz to 100 MHz pixel clock frequency. The DS90UB633A-Q1 device transforms a 10/12-bit wide parallel LVCMOS data bus along with a bidirectional control channel control bus into a single high-speed differential pair. The high-speed serial bit stream contains an embedded clock and DC-balanced information which enhances signal quality to support AC coupling. The DS90UB662-Q1 device receives the single serial data stream and converts it back into a 10/12-bit wide parallel data bus together with the control channel data bus. The DS90UB633A/662 chipsets can accept up to:

• 12-bits of DATA + 2 SYNC bits for an input PCLK range of 56.25 MHz to 100 MHz in the 12-bit mode. Note: No HS/VS restrictions (raw).
• 10/8-bits of DATA + 2 SYNC bits for an input PCLK range of 75 MHz to 100 MHz in the 10/8-bit mode. Note: HS/VS restricted to no more than one transition per 10 PCLK cycles.

The DS90UB633A/662 chipset offer customers the choice to work with different clocking schemes. The DS90UB633A/662 chipsets can use an external oscillator as the reference clock source for the PLL (see Section 7.4.1) or PCLK from the imager as primary reference clock to the PLL (see Section 7.4.2).