The proxy controller timing parameters are based on the REFCLK timing. Timing accuracy for the I2C proxy controller is based on the REFCLK or XTL clock source attached to the DS90UB638-Q1 deserializer. Before REFCLK is applied, the deserializer will default to an internal reference clock with 25-MHz ±10% accuracy. The I2C controller regenerates the I2C read or write access using timing controls in the registers 0xA and 0xB to regenerate the clock and data signals to meet the desired I2C timing in Standard, Fast, or Fast-plus modes of operation.

I2C controller SCL high time is set in register 0x0A[7:0]. This field configures the high pulse width of the SCL output when the serializer is the controller on the local deserializer I2C bus. The default value is set to provide a minimum 5-µs SCL high time with the reference clock at 25 MHz + 100 ppm, including four additional oscillator clock periods or synchronization and response time. Units are 40 ns for the nominal oscillator clock frequency, giving Min_delay = 40 ns × (SCL_HIGH_TIME + 4).

I2C controller SCL low time is set in register 0x0B[7:0]. This field configures the low pulse width of the SCL output when the serializer is the controller on the local deserializer I2C bus. This value is also used as the SDA setup time by the I2C target to provide data before SCL is released during accesses over the bidirectional control channel. The default value is set to provide a minimum 5-µs SCL high time with the reference clock at 25 MHz + 100 ppm, including four additional oscillator clock periods or synchronization and response time. Units are 40 ns for the nominal oscillator clock frequency, giving Min_delay = 40 ns × (SCL_HIGH_TIME + 4). See #GUID-395D500D-105C-4575-999F-561C6300D16F/T4585536-29 example settings for Standard mode, Fast mode, and Fast Mode Plus timing.