ZHCSOU1 February 2023 DS90UB638-Q1
PRODUCTION DATA
A valid 23-MHz to 26-MHz reference clock is required on the REFCLK pin 5 for precise frequency operation. The REFCLK frequency defines all internal clock timers, including the back channel rate, I2C timers, CSI-2 datarate, FrameSync signal parameters, and other timing critical internal circuitry. REFCLK input must be continuous. If the REFCLK input does not detect a transition more than 20 µS, this may cause a disruption in the CSI-2 output. REFCLK should be applied to the DS90UB638-Q1 only when the supply rails are above minimum levels (see GUID-EC19DD5B-2845-409C-8C7E-7905A49CF361.html#GUID-EC19DD5B-2845-409C-8C7E-7905A49CF361). At start-up, the DS90UB638-Q1 defaults to an internal oscillator to generate an backup internal reference clock at nominal frequency of 25 MHz ±10%.
The REFCLK LVCMOS input oscillator specifications are listed in #GUID-555E6390-87D8-4557-9A5D-695BC0B61BF0/SNLS4791032.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| REFERENCE CLOCK | ||||||
| Frequency tolerance | –40°C ≤ TA ≤ 105°C | ±50 | ppm | |||
| Frequency stability | Aging | ±50 | ppm | |||
| Amplitude | 800 | 1200 | V(VDDIO) | mVp-p | ||
| Symmetry | Duty Cycle | 40% | 50% | 60% | ||
| Rise and fall time | 10% – 90% | 5 | ns | |||
| Jitter | 200 kHz – 10 MHz | 50 | 1000 | ps p-p | ||
| Frequency | 23 | 25 | 26 | MHz | ||