The FrameValid (FV) and LineValid (LV) indications from the Receive Port indicate approximate frame and line boundaries at the FPD-Link III Receiver input. These signals may not be accurate if the receiver is in CSI-2 input mode and multiple video streams are present at the Receive Port input. A common example of this scenario would be multiple Virtual Channel IDs received on a single port.

The DS90UB638-Q1 allows setting the polarity of these signals by register programming. The FV and LV polarity are controlled on a per-port basis and can be independently set in the PORT_CONFIG2 register 0x7C.

To prevent false detection of FrameValid, FV must be asserted for a minimum number of clocks prior to first video line to be considered valid. The minimum FrameValid time is programmable in the FV_MIN_TIME register 0xBC.

Figure 7-5 Minimum FV to LV

For other settings of FV_MIN_TIME, the required FV to LV setup in Serializer PCLKs can be determined by:

Absolute Min + (FV_MIN_TIME × Conversion factor)

For other settings of FV_MIN_TIME, the required FV to LV setup in Serializer PCLKs can be determined by:

Absolute Min + (FV_MIN_TIME × Conversion factor)