The CSI-2 Transmitters may operate nominally at 400 or 800 Mbps, or 1.6 Gbps. This operation is controlled through the CSI_PLL_CTL 0x1F register (see Table 7-48). The actual CSI-2 rate is proportional to the REFCLK frequency.

When configuring to 800 Mbps or 1.6 Gbps, the CSI-2 timing parameters are automatically set based on the CSI_PLL_CTL 0x1F register. In the case of alternate settings, the respective CSI-2 timing parameters registers must be programmed, and the appropriate override bit must be set. For the 1.664-Gbps and 1.472-Gbps options, these settings will also affect internal device timing for back channel operation, I2C, Bidirectional Control Channel, and FrameSync operation which scale with the REFCLK frequency.

To operate CSI-2 at speed of 400-Mbps mode, set CSI_PLL_CTL to 11b (0x1F[1:0] =11) to enable 400-Mbps operation for the CSI-2 Transmitters. Internal PLL and Timers are then automatically adjusted for the reduced reference clock frequency. Software control of CSI-2 Transmitter timing registers is required to provide proper interface timing on the CSI-2 Output. The following are the recommended timer settings for 400-Mbps operation.

# Set CSI-2 Timing parameters
WriteI2C(0xB0,0x2)    # set auto-increment, page 0
WriteI2C(0xB1,0x40)   # CSI-2 Port 0
WriteI2C(0xB2,0x83)   # TCK Prep
WriteI2C(0xB2,0x8D)   # TCK Zero
WriteI2C(0xB2,0x87)   # TCK Trail
WriteI2C(0xB2,0x87)   # TCK Post
WriteI2C(0xB2,0x83)   # THS Prep
WriteI2C(0xB2,0x86)   # THS Zero
WriteI2C(0xB2,0x84)   # THS Trail
WriteI2C(0xB2,0x86)   # THS Exit
WriteI2C(0xB2,0x84)   # TLPX