ZHCSOU1 February 2023 DS90UB638-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | PIN OR FREQUENCY | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|---|
| HSTX DRIVER AC SPECIFICATIONS |
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| HSTXDBR | Data bit rate | REFCLK = 23 MHz | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | 368 | 736 | 1472 | Mbps | |
| REFCLK = 25 MHz | 400 | 800 | 1600 | Mbps | ||||
| REFCLK = 26 MHz | 416 | 832 | 1664 | Mbps | ||||
| fCLK | DDR clock frequency | REFCLK = 23 MHz | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | 184 | 368 | 736 | MHz | |
| REFCLK = 25 MHz | 200 | 400 | 800 | MHz | ||||
| REFCLK = 26 MHz | 208 | 416 | 832 | MHz | ||||
| ΔVCMTX(HF) | Common mode voltage variations HF | Common-level variations above 450MHz | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | 15 | mVRMS | |||
| ΔVCMTX(LF) | Common mode voltage variations LF | Common-level variations between 50 and 450MHz | 25 | mVRMS | ||||
| tRHS tFHS | 20% to 80% rise and fall HS | HS bit rates ≤ 1 Gbps (UI ≥ 1 ns) | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | 0.3 | UI | |||
| HS bit rates > 1 Gbps (UI | 0.35 | UI | ||||||
| Applicable for all HS bit rates. However, to avoid excessive radiation, bit rates ≤ 1 Gbps (UI ≥ 1 ns), should not use values below 150 ps | 100 | ps | ||||||
| Applicable for all HS bit rates when supporting > 1.5 Gbps | 0.4 | UI | ||||||
| Applicable for all HS bit rates when supporting > 1.5 Gbps. However, to avoid excessive radiation, bit rates ≤ 1.5 Gbps should not use values below 100 ps and bit rates ≤ 1 Gbps should not use values below 150 ps. | 50 | ps | ||||||
| SDDTX | TX differential return loss | fLPMAX | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | –18 | dB | |||
| fH | HSData rates < 1.5 Gbps | –9 | dB | |||||
| HSData rates > 1.5 Gbps | -4.5 | dB | ||||||
| fMAX | HSData rates < 1.5 Gbps | –-3 | dB | |||||
| HSData rates > 1.5 Gbps | –-2.5 | dB | ||||||
| SCCTX | TX common mode return loss | fLPMAX | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | –20 | dB | |||
| fH | –15 | dB | ||||||
| fMAX | –9 | dB | ||||||
| LPTX DRIVER AC SPECIFICATIONS |
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| tRLP | Rise time LP | 15% to 85% rise time | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | 25 | ns | |||
| tFLP | Fall time LP | 15% to 85% fall time | 25 | ns | ||||
| tREOT | Rise time post-EoT | 30%-85% rise time | 35 | ns | ||||
| tLP-PULSE-TX | Pulse width of the LP exclusive-OR clock | First LP exclusive-OR clock pulse after Stop state or last pulse before Stop state | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | 40 | ns | |||
| All other pulses | 20 | ns | ||||||
| tLP-PER-TX | Pulse width of the LP exclusive-OR clock | 90 | ns | |||||
| DV/DtSR | Slew rate | CLoad = 0pF | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | 500 | mV/ns | |||
| CLoad = 5pF | 300 | mV/ns | ||||||
| CLoad = 20pF | 250 | mV/ns | ||||||
| CLoad = 70pF | 150 | mV/ns | ||||||
| CLoad = 0 to 70pF (Falling Edge Only) Data rate < 1.5 Gbps | 30 | mV/ns | ||||||
| CLoad = 0 to 70pF (Rising Edge Only) Data rate < 1.5 Gbps | 30 | mV/ns | ||||||
| CLoad = 0 to 70pF (Falling Edge Only) Data rate > 1.5 Gbps | 25 | mV/ns | ||||||
| CLoad = 0 to 70pF (Rising Edge Only) Data rate > 1.5 Gbps | 25 | mV/ns | ||||||
| CLoad = 0 to 70pF (Rising Edge Only) Applicable when the supported Data rate is < 1.5 Gbps | 0 - 0.075 × (VO,INST - 700) | mV/ns | ||||||
| CLoad = 0 to 70pF (Rising Edge Only) Applicable when the supported Data rate is > 1.5 Gbps | 25 - 0.0625 × (VO,INST - 550) | mV/ns | ||||||
| CLOAD | Load capacitance | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | 0 | 50 | pF | |||
| DATA-CLOCK TIMING SPECIFICATIONS |
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| UIINST | UI instantaneous | In 1, 2, 3, or 4 Lane Configuration | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | 0.6 | 2.7 | ns | ||
| ΔUI | UI variation | UI ≥ 1ns | -10% | 10% | UI | |||
| 0.667ns ≤ UI | -5% | 5% | UI | |||||
| tSKEW(TX) | Data to Clock Skew (measured at transmitter) Skew between clock and data from ideal center | Data rate ≤ 1 Gbps | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | -0.15 | 0.15 | UIINST | ||
| Data rate: 1 Gbps to 1.5 Gbps | -0.2 | 0.2 | UIINST | |||||
| tSKEW(TX)STATIC | Static Data to Clock Skew (TX) | Data rate > 1.5 Gbps | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | -0.2 | 0.2 | UIINST | ||
| tSKEW(TX)DYNAMIC | Dynamic Data to Clock Skew (TX) | -0.15 | 0.15 | UIINST | ||||
| ISI | Channel ISI | 0.2 | UIINST | |||||
| CSI-2 TIMING SPECIFICATIONS |
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| tCLK-MISS | Timeout for receiver to detect absence of clock transitions and disable the clock lane HS-RX | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | 60 | ns | ||||
| tCLK-POST | HS exit | 60 + 52×UI | ns | |||||
| tCLK-PRE | Time HS clock shall be driver prior to any associated data lane beginning the transition from LP to HS mode | 8 | UI | |||||
| tCLK-PREPARE | Clock lane HS entry | 38 | 95 | ns | ||||
| tCLK-SETTLE | Time interval during which the HS receiver shall ignore any clock lane HS transitions | 95 | 300 | ns | ||||
| tCLK-TERM-EN | Time-out at clock lane display module to enable HS termination | Time for Dn to reach VTERM-EN | 38 | ns | ||||
| tCLK-TRAIL | Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst | 60 | ns | |||||
| tCLK-PREPARE + tCLK-ZERO | TCLK-PREPARE + time that the transmitter drives the HS-0 state prior to starting the clock | 300 | ns | |||||
| tD-TERM-EN | Time for the data lane receiver to enable the HS line termination | CSI_D0P/N, CSI_D1P/N, CSI_D2P/N, CSI_D3P/N, CSI_CLK0P/N, CSI_CLK1P/N | Time for Dn to reach VTERM-EN | 35 + 4×UI | ns | |||
| tEOT | Transmitted time interval from the start of tHS-TRAIL to the start of the LP-11 state following a HS burst | 105 + 12×UI | ns | |||||
| tHS-EXIT | Time that the transmitter drives LP-11 following a HS burst | 100 | ns | |||||
| tHS-PREPARE | Data lane HS entry | 40 + 4×UI | 85 + 6×UI | ns | ||||
| tHS-PREPARE + tHS-ZERO | tHS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence | 145 + 10×UI | ns | |||||
| tHS-SETTLE | Time interval during which the HS receiver shall ignore any data lane HS transitions, starting from the beginning of tHS-SETTLE | 85 + 6×UI | 145 + 10×UI | ns | ||||
| tHS-SKIP | Time interval during which the HS-RX should ignore any transitions on the data lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. | 40 | 55 + 4×UI | ns | ||||
| tHS-TRAIL | Data lane HS exit | 60 + 4×UI | ns | |||||
| tLPX | Transmitted length of LP state | 50 | ns | |||||
| tWAKEUP | Recovery Time from Ultra Low Power State (ULPS) | 1 | ms | |||||
| tINIT | Initialization period | 100 | µs | |||||