The following interrupts are available for each CSI-2 Transmit Port:

• Pass indication
• Synchronized status
• Deassertion of Pass indication for an input port assigned to the CSI-2 TX Port
• Loss of Synchronization between input video streams
• RX Port Interrupt – interrupts from RX Ports mapped to this CSI-2 Transmit port

See the CSI_TX_ICR address 0x36 (Table 7-72) and CSI_TX_ISR address 0x37 (Table 7-73) registers for details.

The setting of the individual interrupt status bits is not dependent on the related interrupt enable controls. The interrupt enable controls whether an interrupt is generated based on the condition, but the enable does not prevent the interrupt status assertion.