ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
For the typical design application, use the parameters listed in Table 8-4.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
VDDIO | 1.8 V or 3.3 V |
VDD11 | 1.1 V |
VDD18 | 1.8 V |
AC Coupling Capacitor for STP with DS90UB63x CSI-2 Serializer: RIN[3:0]± | 33 nF - 100 nF (50V/X7R/0402) |
AC Coupling Capacitor for Coaxial with DS90UB63x CSI-2 Serializer: RIN[3:0]+ | 33 nF - 100 nF (50V/X7R/0402) |
AC Coupling Capacitor for Coaxial with DS90UB63x CSI-2 Serializer: RIN[3:0]- | 15 nF - 47 nF (50V/X7R/0402) |
AC-Coupling Capacitor for STP with DS90UB633A-Q1: RIN[3:0]± | 100 nF (50V/X7R/0402) |
AC-Coupling Capacitor for Coaxial with DS90UB633A-Q1: RIN[3:0]+ | 100 nF (50V/X7R/0402) |
AC-Coupling Capacitor for Coaxial with DS90UB633A-Q1: RIN[3:0]- | 47 nF (50V/X7R/0402) |
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme. External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in Figure 8-6. For applications using single-ended 50-Ω coaxial cable, terminate the unused data pins (RIN0–, RIN1–, RIN2–, RIN3–) with an AC-coupling capacitor and a 50-Ω resistor.
For high-speed FPD–Link III transmissions, use the smallest available package for the AC-coupling capacitor to help minimize degradation of signal quality due to package parasitics.