ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
RX port-specific register. The FPD-Link III Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7 | CSI_WAIT_FS1 | R/W | 0 | CSI-2 Wait for FrameStart packet with count 1 The CSI-2 Receiver will wait for a Frame Start packet with count of 1 before accepting other packets This bit has no effect in RAW FPD3 input modes. |
6 | CSI_WAIT_FS | R/W | 1 | CSI-2 Wait for FrameStart packet CSI2 Receiver will wait for a Frame Start packet before accepting other packets This bit has no effect in RAW FPD3 input modes. |
5 | CSI_FWD_CKSUM | R/W | 1 | Forward CSI-2 packets with checksum errors 0: Do not forward errored packets 1: Forward errored packets This bit has no effect in RAW FPD3 input modes. |
4 | CSI_FWD_ECC | R/W | 1 | Forward CSI-2 packets with ECC errors 0: Do not forward errored packets 1: Forward errored packets |
3 | DISCARD_1ST_LINE _ON_ERR / CSI_FWD_LEN | R/W | 1 | In RAW Mode, Discard first video line if FV to LV setup time is not met. 0 : Forward truncated 1st video line 1 : Discard truncated 1st video line In FPD3 CSI-2 Mode, Forward CSI-2 packets with length errors 0: Do not forward errored packets 1: Forward errored packets |
2 | RESERVED | R/W/S | Strap | Reserved. |
1:0 | FPD3_MODE | R/W/S | Strap | FPD3 Input Mode 00: Reserved 00: Reserved 01: RAW12 Low Frequency Mode (DS90UB633A-Q1 compatible) 10: RAW12 High Frequency Mode(DS90UB633A-Q1 compatible) 11: RAW10 Mode (DS90UB633A-Q1 compatible) |